RU41170U1 - DIGITAL RANGE ASSESSMENT DEVICE - Google Patents

Abstract

A digital range estimation device relates to digital computing and can be used in radar systems (radar) in devices for measuring radial speed and range of a target. The technical result is a simplification of the scheme, reducing the volume of hardware implementation, the complexity and cost of the device while maintaining the high quality of the radar. The device contains the first and second analog-to-digital converters, the inputs of which are combined and are the input of the device, and the outputs are connected respectively to the inputs of the first and second storage devices, a digital signal processing processor, a digital signal processing processor module for a rough range estimation (DSP module), a shaper a cyclic signal comprising serially connected a first adder, a third storage device and a second adder. The output of the first storage device is connected to the first inputs of the first adder of the cyclic signal generator and the DSP module, and the output of the second storage device is connected to their second inputs. The output of the second adder of the cyclic signal generator is connected to the first input of the digital signal processor, the first output of which is connected to the first output of the DSP module, the second output of which and the output of the digital signal processor are the first and second outputs of the device, respectively.

Description

The utility model relates to digital computing and can be used in radar systems (radar) in devices for measuring radial speed and range of a target.

As devices whose output information is used in the radar for measuring radial speed and target range, specialized multiprocessor computer systems (SMVK) of multi-channel digital signal processing containing a large number of digital signal processing processors (DSPs) are widely used. DSPs are designed to perform fast Fourier transforms (FFT) or Hartley transforms (BPH), calculate spectral density functions, calculate fast digital convolution functions and analyze them for exceeding specified thresholds. Modern SMVKs, as a rule, consist of modules based on DSP (ADSP, Motorola, TMS), produced in various formats (PCI, VME, PMC) and designs (commercial, industrial, military), differ from one another, mainly, in composition equipment depending on the purpose and technical characteristics (TX) of the radar.

The closest in technical essence to a utility model (prototype) is a digital signal processing device containing an amplitude-to-digital converter, the input of which is the input of the device and connected to the output of the band-pass filter of the total channel of the radar receiver, and the output is connected to a storage device, to the output of which is connected SMVK, the output of which is the output of the device, while SMVK consists of a DSP module for a rough estimate of the range and DSP modules for an accurate estimate of the range, and the total number M Ts Pic is estimated by the ratio

where ΔТ is the time interval of the sensing cycles;

Δt is the FFT counting time (FFT) of the number of samples equal to N.

In this device, the following is performed: the formation of an array of m - bit numbers of length L (the bit capacity of t is determined by the type of ADC used, the value of L is determined by the intervals of digitization and strobe of the radar receiver); partitioning this array into M overlapping arrays of length N (N is the number of samples of the probe signal, M = LI (NP \ where P is the number of samples in the overlap interval); calculating the spectrum of each of the overlapping arrays and processing it (determining the magnitude and number of the reference maximum , comparing it with a threshold). In case of detection of reflected

the signal is measured at the radial speed and a rough estimate of the radial range of the target is made (at half overlap P = N / 2, if the probe signal is harmonic). In case of detection and obtaining an accurate estimate of the target radial range, fast convolution of each array is calculated with an array of adjusted reference function, which is the numerical equivalent of the probing (reference) signal corrected for the Doppler frequency (determining the value and number of the reference maximum, comparing it with a threshold) . For probing signals such as LFM, FKM, the overlap corresponds to P = 1. Thus, the device forms a sign of target detection when thresholds are exceeded by maximum values and provides, respectively, to setting the value of P to estimate the target range [L. Rabiner, B. Gould, “Theory and application of digital signal processing”. M. "WORLD", 1978. P. 803, Fig. 13.9].

The reason that impedes the achievement of the technical result indicated below when using the known digital signal processing device is as follows.

One of the properties of cyclic convolution is that for N samples of the input signal and the reference signal, among N samples of the output signal, only one corresponds to linear convolution, i.e. only one exit count is “correct,” and all the rest are “wrong.” In order to obtain all samples of the linear convolution signal using cyclic convolution, the number of samples of the input signal must be expanded, i.e. double, while increasing the number of support functions to the same value by adding zero samples. Therefore, to determine the exact range (corresponding to the digitization interval), it is necessary to perform a cyclic convolution with the number of samples equal to 2N. Direct calculation of a convolution of length 2N leads to a 3 dB degradation in the signal-to-noise ratio, an increase in computation time by a factor of 2, and uncertainty in the choice of a threshold. For most real-time radars, such losses are unacceptable, therefore, in practice, the method of parallel calculation of N convolutions of length N is implemented. The need to calculate a large number of functions of digital linear convolution at limited time intervals leads to the need to distribute their calculations on parallel computing structures - multiprocessor systems, which complicates and increases the cost of digital range estimation devices in radars.

The objective of the utility model is to simplify the circuit, reduce the amount of hardware implementation, the complexity and cost of the digital range estimation device while maintaining the high quality of the radar.

The specified technical result is achieved by the fact that in the known device for digital signal processing, containing the first analog-to-digital Converter,

the input of which is the input of the device, and the output is connected to the input of the first storage device, a module of digital signal processing processors for rough range estimation (DSP module), a digital signal processing processor, according to a utility model, a second analog-to-digital converter, a second storage device, a cyclic shaper are introduced the signal containing a series-connected first adder, a third storage device and a second adder, while the input of the second analog-to-digital Converter is connected to the input of the first analog-to-digital converter, and the output is connected to the input of the second storage device, the output of the first storage device is connected to the first inputs of the first adder of the cyclic signal generator and the DSP module, and the output of the second memory device is connected to the second inputs of the first adder of the cyclic signal generator and DSP module, the output of the second adder of the cyclic signal shaper is connected to the first input of the digital signal processor, to the second input of which connecting a first output of DSP module, the second output and the output of which the digital signal processor are, respectively, first and second outputs of the device.

The utility model is illustrated by drawings, in which: FIG. 1 is a block diagram of a digital range estimation device; FIG. 2 is a mathematical model of a cyclic signal generator, FIG. 3 is a graphical model of a cyclic signal generator, FIG. 4 is a flowchart of a fast cyclic convolution calculation algorithm and its processing, FIG. 5 is a graphical illustration of calculations performed by the DSP module of a rough range estimate .

The digital range estimation device (Fig. 1) contains the first 1 and second 2 analog-to-digital converters (ADCs), the first 3 and second 4 storage devices (memory), a cyclic signal shaper (FCS) 5, containing the first adder 6 connected in series, the third Memory 7 and the second adder 8; digital signal processing processor (DSP) 9 and a module of digital signal processing processors for rough range estimation (DSP module) 10. The inputs of the first 1 and second 2 ADCs are combined and, being the input of the device, are connected to the output of the band-pass filter of the total channel of the radar receiver, and their the outputs are connected to the inputs of the first 3 and second 4 memory, respectively. The output of the first memory 3 is connected to the first inputs of the first adder 6 FCS 5 and the DSP module 10, and the output of the second memory 4 is connected to the second inputs of the first adder 6 FCS 5 and the DSP module 10. The output of the second adder 8 FCS 5 is connected to the first input of the DSP 9, to the second input of which the first output of the DSP module 10 is connected. Its second output and the output of the DSP module 9 are, respectively, the first and second outputs of the digital range estimator, to which they are connected

consumers of information.

Elements and blocks of the device are typical, made and operate according to well-known rules. For example, ADCs of the AD6645 type can be used as ADCs; as a DSPC 9, an ADSP-TS101 type DSP can be used, and as a DSP module 10, a PCI DSP type 4 × ADSP-TS101 Tiger SHARC from Analog Devices can be used [see, for example, www.rtsoft.ru/dsp]. FCS 5 can be performed on FPGAs of the type EP1810 from ALTERA [see, for example, www.Altera.com].

A digital device for assessing the range works as follows (figure 1).

With a sounding clock frequency, the inputs from the output of the band-pass filter of the total channel of the radar receiver are received at the inputs of the first 1 and second 2 ADCs, containing the useful signal reflected from the target, noise and noise, limited in time by the time-controlled receiver strobe. The sequence of digital samples received from the outputs of the ADC are stored in the first 3 and second 4 memories, respectively. These samples are coherent samples, the summation of which, according to the known rules of statistics, allows you to get one sample with a signal-to-noise ratio increased by 3 dB. In the case of an unmodulated sounding signal, during each probe cycle, the numerical samples stored in the previous probe cycle are processed by the DSP module 10, and in the case of a modulated signal, FPS 5 and DSP 9 are processed sequentially.

If the probe signal is not modulated (harmonic), then coherent samples from memory 3 and 4 of length L are sent to the DSP module 10, where, according to well-known rules (Fig. 5), sequences of numbers with a length equal to the number of samples of the probe signal N are formed Each received array is subjected to FFT or FFT with subsequent calculation of the Fourier spectral density function. The magnitude and coordinates of the threshold excess of each spectral density function are determined, which determine the sign of the presence of a signal reflected from the target in the strobe, the Doppler frequency offset and the position of two sequences containing samples of the reflected signal — the interval of linear convolutions. This information is the output of this block of the central processing unit 10 and from its second output (the first output of the device) is fed to consumers of information.

If the probe signal is modulated (linear frequency modulation or phase-code modulation), then coherent samples a and b of 2N samples length from the outputs of the first 3 and second 4 memories, respectively, are fed to FTSS 5 (figure 2). In the first adder 6, they are summed by the formula moreover, as a result of addition of two coherent

sequences increases the signal-to-noise ratio by 3 dB. The resulting values in an amount equal to twice the number of samples of the signal are recorded in the third memory 7. This sequence is split in half (Fig. 3) and the resulting sequences of numbers with a length equal to the number of samples of the probe signal N are received in the second adder 8, in which the element the addition of the first and second halves recorded in the third memory 7, according to the formula in this way, a cyclic signal is generated with the number of samples equal to the number of samples of the adjusted reference signal, and the signal-to-noise ratio is reduced by 3 dB. The resulting sequence d is fed to the input of the DSPC 9, in which, according to the well-known rules, fast cyclic convolution calculations and its processing are performed (Fig. 4). For example, the calculation of fast cyclic convolution can be performed according to the formula

Z = FFT (FFT (X); FFT (7)),

where X is a cyclic signal;

Y is the reference signal with a frequency spectrum corrected for the Doppler shift;

FFT - Fast Fourier Transform.

In DSPC 9, an algorithm for fast digital convolution of the cyclic and adjusted reference signals is implemented using fast Fourier or Hartley algorithms. The values of the values and coordinates of the threshold excess of convolution values are determined with an accuracy of reference (digitization interval), which are the output information of DSPC 9, which from its output (the second output of the device) goes to information consumers.

Thus, the implementation of the utility model provides a significant simplification of the structural diagram of a digital range estimation device, reducing the complexity and volume of hardware implementation, as well as the cost of the device while maintaining the high quality of the radar. The use of the fast Hartley transform for performing cyclic convolution does not require devices for generating quadrature channels; it helps to obtain a simpler form of program code, which also simplifies the device as a whole.

Claims (1)

A device for digital signal processing, characterized in that it contains a first analog-to-digital converter, the output of which is connected to the input of the first storage device, a second analog-to-digital converter, the output of which is connected to the input of the second storage device, a digital signal processing processor, a module of digital processing processors signals for a rough range estimation (DSP module), a cyclic signal shaper containing the first adder connected in series, the third one is stored e device and a second adder, while the inputs of the first and second analog-to-digital converters are combined and are the input of the device, the output of the first storage device is connected to the first inputs of the first adder of the cyclic signal generator and the DSP module, and the output of the second storage device is connected to the second inputs of the first adder of the cyclic signal shaper and the DSP module, the output of the second adder of the cyclic signal shaper is connected to the first input of the digital signal processor , to the second input of which the first output of the DSP module is connected, the second output of which and the output of the digital signal processor are the first and second outputs of the device, respectively.