RU2642337C1 - Bipolar-field operating amplifier - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: bipolar-field operating amplifier contains an input differential stage (1), a power supply bus, a field effect transistor, a static mode stabilizing circuit (17) connected to the power supply bus, an output bipolar transistor.

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EFFECT: extending the change range of the negative output voltage of the operating amplifier to the level close to the voltage on the second power supply bus and increasing the attenuation factor of the input common-mode signals of the operating amplifier.

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Description

The invention relates to the field of electronics and can be used as a precision signal amplification device.

In modern electronic equipment, operational amplifiers (op amps) are used on field and bipolar transistors, in which the output voltages of the input cascode differential cascade are not at the drains, but at the sources of the output transistors [1-5]. They have a number of advantages (in comparison with classical op amps) in terms of the range of operating frequencies, the level of nonlinear distortion, speed, etc. The inventive op-amp refers to this subclass of devices.

To work in outer space conditions, experimental physics requires precision radiation-resistant op-amps with an extended range of output voltage changes at low-voltage power supply and an increased attenuation coefficient of input common-mode signals. World experience in designing devices of this class shows that the solution to these problems is possible using a bipolar field process [6], which provides the formation of p-channel field and high-quality npn bipolar transistors with radiation resistance up to 1 Mrad and a neutron flux up to 10 ¹³ n / cm ² . However, for such an op-amp, a special circuitry is needed that takes into account the limitations of bipolar field technology [6-10].

The closest prototype (Fig. 1) of the claimed device is the operational amplifier according to the patent US 5.218.319 (in addition, this structure is presented in patents US 6.756.847 fig. 1, US 5.914.639). It contains (Fig. 1) the input differential stage 1, the common source circuit of which 2 is connected to the first 3 bus of the power source, the first 4 and second 5 inputs of the input differential stage 1, the first 6 current output of the input differential stage 1, connected to the source of the first 7 the output field-effect transistor and the base of the first 8 output bipolar transistor, the second 9 current output of the input differential stage 1, connected to the source of the second 10 output field-effect transistor and the base of the second 11 output bipolar transistor, 12th power supply bus, which is connected to the combined drains of the first 7 and second 10 output transistors, a dynamic load circuit 13, the input of which 14 is connected to the collector of the second 11 output bipolar transistor, and the output 15 is connected to the output of the device 16 and connected to the collector of the first 8 output bipolar transistor, a resistive circuit for establishing a static mode 17, connected to the second 12 bus power supply, the first input 18 of which is connected to the emitter of the first 8 output bipolar transistor, and the second input 19 under is connected to the emitter of the second 11 output bipolar transistor, and the gates of the first 7 and second 10 output transistors are connected to each other.

, что особенно проявляется при низковольтном питании (2,5÷3 В). Кроме этого, известная схема ОУ не обеспечивает также высокое ослабление входных синфазных сигналов и характеризуется повышенной нестабильностью статического режима транзисторов.A significant disadvantage of the known op-amp is that it does not provide a wide range of changes in the negative output voltage

, which is especially manifested with low-voltage power supply (2.5 ÷ 3 V). In addition, the well-known op-amp circuitry also does not provide high attenuation of input common-mode signals and is characterized by increased instability of the static mode of transistors.

ОУ до уровня, близкого к напряжению на второй 12 шине источника питания.The main objective of the invention is to expand the range of variation of the negative output voltage

Shelter to a level close to the voltage on the second 12 bus power source.

An additional task is to increase the attenuation coefficient of the input common-mode signals (K _OS.sf ) of the OS.

The objectives are achieved in that in the operational amplifier of FIG. 1, containing the input differential stage 1, the common source circuit of which 2 is connected to the first 3 bus of the power source, the first 4 and second 5 inputs of the input differential stage 1, the first 6 current output of the input differential stage 1, connected to the source of the first 7 output field-effect transistor and the base of the first 8 output bipolar transistor, the second 9 current output of the input differential stage 1, connected to the source of the second 10 output field-effect transistor and the base of the second 11 output bipolar transistor, the second 12 inu of the power source, which is connected to the combined drains of the first 7 and second 10 output transistors, a dynamic load circuit 13, the input of which 14 is connected to the collector of the second 11 output bipolar transistor, and the output 15 is connected to the output of the device 16 and connected to the collector of the first 8 output bipolar a transistor, a resistive circuit for establishing a static mode 17, connected to the second 12 bus of the power source, the first input of which 18 is connected to the emitter of the first 8 output bipolar transistor, and the second input 19 is connected n to the emitter of the second 11 output bipolar transistor, and the gates of the first 7 and second 10 output transistors are connected to each other, new elements and connections are provided - the first 20 and second 21 additional bipolar transistors are introduced into the circuit, the base of the first 20 additional bipolar transistor is connected to the base the first 8 output bipolar transistor, the emitter of the first 20 additional bipolar transistor is connected to the emitter of the first 8 output bipolar transistor, the collector of the first 20 additional bipolar the transistor is connected to the gate of the first 7 output field-effect transistor, the base of the second 21 additional bipolar transistor is connected to the base of the second 11 output bipolar transistor, the emitter of the second 21 additional bipolar transistor is connected to the emitter of the second 11 output bipolar transistor, the collector of the second 21 additional bipolar transistor the second 10 output field-effect transistor, and the combined gates of the first 7 and second 10 output field-effect transistors are connected to the first 3 bus power supply through an additional current-stabilizing two-terminal 22.

In FIG. 1 shows a diagram of an op-amp prototype, and in FIG. 2 is a diagram of the inventive device in accordance with the claims.

In FIG. 3 shows particular variants of the resistive circuit establishing a static mode 17.

In FIG. 4 is a diagram of an op-amp; FIG. 2, in the environment PSpice on radiation-dependent models of integrated transistors ABMK_1_3 NPO Integral (Minsk).

In FIG. 5 shows the frequency response of the adjusted opamp of FIG. 4 without feedback when the resistance of the resistor 29 (Fig. 3a) R29 = 250 Ohms (or in the notation of Fig. 4 - R1 = 250 Ohms).

In FIG. 6 shows the frequency response of the opamp of FIG. 4 without feedback when the resistance of the resistor 29 (Fig. 3a) R29 = 1 Ohm (or in the notation of Fig. 4 - R1 = 250 Ohm).

Computer simulation shows that in the claimed circuit emitters of transistors 8, 11, 20, 21 can, in the particular case, have the potential of the second 12 bus power source. In this case, the main parameters of the op-amp do not degrade, and the maximum amplitude of the negative output voltage of the op-amp is close to the voltage on the second 12 bus of the power source.

The bipolar field operational amplifier of FIG. 2 contains an input differential cascade 1, the common source circuit of which 2 is connected to the first 3 bus of the power supply, the first 4 and second 5 inputs of the input differential cascade 1, the first 6 current output of the input differential cascade 1, connected to the source of the first 7 output field-effect transistor and the base the first 8 output bipolar transistor, the second 9 current output of the input differential stage 1, connected to the source of the second 10 output field-effect transistor and the base of the second 11 output bipolar transistor, the second 12 buses at the power source, which is connected to the combined drains of the first 7 and second 10 output transistors, a dynamic load circuit 13, the input of which 14 is connected to the collector of the second 11 output bipolar transistor, and the output 15 is connected to the output of the device 16 and connected to the collector of the first 8 output bipolar a transistor, a resistive circuit for establishing a static mode 17 connected to a second 12 bus of a power source, the first input of which 18 is connected to the emitter of the first 8 output bipolar transistor, and the second input 19 is connected to the emitter of the second 11 output bipolar transistor, and the gates of the first 7 and second 10 output transistors are connected to each other. The first 20 and second 21 additional bipolar transistors are introduced into the circuit, the base of the first 20 additional bipolar transistor is connected to the base of the first 8 output bipolar transistor, the emitter of the first 20 additional bipolar transistor is connected to the emitter of the first 8 output bipolar transistor, the collector of the first 20 additional bipolar transistor is connected to the gate of the first 7 output field-effect transistor, the base of the second 21 additional bipolar transistor is connected to the base of the second 11 output bipolar the transistor, the emitter of the second 21 additional bipolar transistor is connected to the emitter of the second 11 output bipolar transistor, the collector of the second 21 additional bipolar transistor is connected to the gate of the second 10 output field-effect transistor, and the combined gates of the first 7 and second 10 output field-effect transistors are connected to the first 3 source bus power supply through an additional current-stabilizing two-terminal 22.

In FIG. 2 input differential stage 1 is implemented on the input field-effect transistors 23, 24 and the reference current source 25.

In the particular case, the resistive circuit for establishing the static mode 17 may contain auxiliary resistors 26, 27 and 28 (Fig. 3a) or one auxiliary resistor 29 (Fig. 3b).

To reduce the output resistance of the op-amp to the output 16 of the circuit, FIG. 2, a buffer amplifier Gain = 1 can be connected (Fig. 4).

Consider the operation of the op-amp, FIG. 2.

The static mode of the transistors of the circuit, FIG. 2, is set by the reference current sources 25 and 22. In this case, the drain currents (I _ci ) and collector currents (I _ki ) of the transistors of the circuit are determined taking into account local negative feedback by the Kirchhoff equations:

where I ₂₅ , I ₂₂ are the currents of the reference current source 25 and the additional current-stabilizing two-terminal 22.

The differential voltage gain of the op-amp circuit of FIG. 2 is determined by the product:

where u _vyh.16 - increment opamp output voltage at node 16 caused by change in the voltage (u = u _{vh.4.5 Rin.)} between the inputs 4 and 5, the OS;

- коэффициент преобразования напряжения между входами 4

- voltage conversion coefficient between inputs 4

and 5 op-amps (u _input ) into the voltage between the first 6 and second 9 current outputs of the input differential stage 1;

- коэффициент передачи дифференциального напряжения u_9-6 между узлами 9 и 6 на выход ОУ 16.

- the transmission coefficient of the differential voltage u _9-6 between nodes 9 and 6 to the output of the OS 16.

Moreover

where R _{equiv. 9-6} is the equivalent differential resistance between nodes 9 and 6;

R _ekv.16 - equivalent impedance in the high impedance output node 16 OS.

Moreover, in formulas (9) and (10):

Where S ₂₃ , S ₂₄ - the steepness of the drain characteristics of the corresponding field-effect transistors 23, 24;

R ₂₈ is the resistance of the resistor 28;

r _e11 = r _e8 = ϕ _t / I ₀ - resistance of the emitter junctions of transistors 11 and 8;

ϕ _t = 25 mV - temperature potential.

The numerical value of the equivalent resistance R _{equiv. 16 is} close to the resistances of the closed collectors of the transitions of the output transistors of the dynamic load circuit 13, made in the form of a current mirror, and the transistor 8, and the resistance R _{equiv. 9-6} is determined mainly by the input resistance of the source circuit of the field-effect transistors 7 and 10:

As a result, the voltage gain of the open op-amp, FIG. 2, it turns out quite large (≈10 ³ , Fig. 6).

In the claimed op-amp circuit (in comparison with the prototype), the attenuation coefficient of the input common-mode signals (K _os.sf ) is also increased. This effect is explained by the increased symmetry of the op amp circuit of FIG. 2 and the introduction due to new elements of negative feedback on the common mode signal in the output circuit of the input differential stage 1 (transistors 21 and 20) [11].

Due to the high symmetry of the op-amp circuit and the introduction of negative feedback, the zero bias voltage of the claimed op-amp (U _cm ) is measured in microvolts (provided that the transistors used are identical and have an ideal current mirror 13).

Computer simulation shows that in the claimed circuit emitters of transistors 8, 11, 20, 21 can, in the particular case, have the potential of the second 12 bus power source. In this case, the main parameters of the op-amp do not degrade, and the maximum amplitude of the negative output voltage of the op-amp is close to the voltage on the second 12 bus of the power source.

Thus, the claimed device has significant advantages compared to the op-amp prototype.

 Sources and Information

1. Patent US 5.218.319, fig. 1, fig. 3a.

2. Patent US 7.639.079, fig. 10.

3. US Pat. No. 6,756,847, fig. one.

4. Patent US 7.142.056, fig. one.

5. Patent US 5.914.639.

6. The elemental base of radiation-resistant information-measuring systems: monograph / N.N. Prokopenko, O.V. Dvornikov, S.G. Krutchinsky; under the general. ed. Doctor of Technical Sciences prof. N.N. Prokopenko; FSBEI HPE “South-Ros. state un-t economics and service. " - Mines: FSBEI HPE "URGUES", 2011. - 208 p.

7. Problems of designing analog devices with input field effect transistors. Part 1 / O. Dvornikov // Components and Technologies, No. 6, 2005, http://kit-e.ru/articles/device/2005_6_218.php.

8. Problems of designing analog devices with input field effect transistors. Part 2 / Oh. Dvornikov // Components and Technologies, No. 7, 2005, http://kit-e.ru/articles/device/2005_7_216.php.

9. Problems of designing analog devices with input field effect transistors. Part 3 / O. Dvornikov // Components and Technologies, No. 8, 2005, http://kit-e.ru/articles/device/2005_8_184.php.

10. Circuitry of bipolar-field analog circuits. Part 4. Current sources for special applications / O. Dvornikov // Chip News, No. 3 (96), 2005. - P. 66-68.

11. Architecture and circuitry of differential amplifiers with increased attenuation of common-mode signals: monograph / N.N. Prokopenko, S.V. Hooks. - Mines: GOU VPO "YURGUES", 2008. - 329 p.

Claims (1)

A bipolar-field operational amplifier containing an input differential stage (1), the common source circuit of which (2) is connected to the first (3) bus of the power source, the first (4) and second (5) inputs of the input differential stage (1), the first ( 6) the current output of the input differential stage (1), connected to the source of the first (7) output field-effect transistor and the base of the first (8) output bipolar transistor, the second (9) current output of the input differential stage (1), connected to the source of the second (10) ) output field effect transistor and base a second (11) output bipolar transistor, a second (12) power supply bus, which is connected to the combined drains of the first (7) and second (10) output transistors, a dynamic load circuit (13), the input of which (14) is connected to the collector of the second ( 11) the output bipolar transistor, and the output (15) is connected to the output of the device (16) and connected to the collector of the first (8) output bipolar transistor, the resistive circuit for establishing the static mode (17), connected to the second (12) bus of the power supply, the first input (18) which is connected to the emitter the first (8) output bipolar transistor, and the second input (19) is connected to the emitter of the second (11) output bipolar transistor, and the gates of the first (7) and second (10) output transistors are connected to each other, characterized in that the circuit is introduced the first (20) and second (21) additional bipolar transistors, the base of the first (20) additional bipolar transistor is connected to the base of the first (8) output bipolar transistor, the emitter of the first (20) additional bipolar transistor is connected to the emitter of the first (8) output bip the transistor, the collector of the first (20) additional bipolar transistor is connected to the gate of the first (7) output field effect transistor, the base of the second (21) additional bipolar transistor is connected to the base of the second (11) output bipolar transistor, the emitter of the second (21) additional bipolar transistor is connected with the emitter of the second (11) output bipolar transistor, the collector of the second (21) additional bipolar transistor is connected to the gate of the second (10) output field-effect transistor, The first gates of the first (7) and second (10) output field-effect transistors are connected to the first (3) bus of the power supply through an additional current-stabilizing two-terminal device (22).

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