RU2635278C1 - Digital frequency synthesizer with high linearity of law of frequency variation - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: digital frequency synthesizer (DFS) with high linearity of the law of frequency variation contains (Fig. 1) the first memory register 1, the code multiplier 2, the digital storage 3, the code-to-sinus functional converter 4, the digital-to-analogue converter (DAC) 5, the bandpass filter 6, the second memory register 7, the binary counter 8, the reference generator 9, formation and delay unit 10. The digital inputs of the DFS are the inputs of the first and second memory registers, and its analogue output is the output of the bandpass filter.

EFFECT: increase in the linearity of the law of frequency variation of the synthesizer, and the synthesized frequency band is higher than the clock frequency.

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Description

The invention relates to electronic computing and radio engineering, is intended for the synthesis of frequency-modulated (FM) signals and can be used in radar and communication systems.

Known digital synthesizers of frequency and phase-modulated signals containing a reference generator and a delay unit, a first memory register, a first digital memory, a second memory register, a second digital memory, adder, code converter, DAC, low-pass filter, a third memory register, a divider with a variable division ratio , fourth memory register, third digital storage device [1].

The closest technical solution (prototype) to the proposed one is a digital frequency synthesizer containing a reference generator, a delay unit, a first ROM unit, a first digital drive, a second memory register, a second digital drive, a code converter, DAC, low-pass filter, a second ROM unit and a counter with preset [2].

However, the known DSC and DAC do not have increased speed. The invention allows to increase the linearity of the law of changing the frequency of the synthesizer and to form complex frequency-modulated signals with a band of synthesized frequencies above the clock frequency.

A positive technical result - increasing the linearity of the law of changing the frequency of the synthesizer, and the synthesized frequency band above the clock frequency - is achieved due to the fact that the digital frequency synthesizer contains a reference generator and a block for generating and delaying in series, the first and second memory registers, a binary counter, digital drive and DAC; the output of the second memory register is connected to the input of the binary counter, the outputs of the block of formation and delay are connected to the clock inputs of a digital drive, binary counter and DAC, and new is that the block of formation and delay is made in the form of a block of formation of clock pulses in the form of a "meander", and also introduced a code multiplier, a functional code-sine converter, a bandpass filter; the output of the first memory register is connected to the first input of the code multiplier, the second input of the code multiplier is connected to the output of the binary counter; and the output of the code multiplier is connected to the input of the digital storage device, the output of the latter is connected to the input of the code-sine functional converter, its output is connected to the information input of the DAC, the outputs of the generation and delay unit are connected to the three clock inputs of the code multiplier.

A digital frequency synthesizer with a high linearity of the law of frequency variation contains (Fig. 1) a first memory register 1, a code multiplier 2, a digital drive 3, a code-sine function converter 4, a digital-to-analog converter 5, a band-pass filter 6, a second memory register 7, a binary counter 8, the reference generator 9, the formation and delay unit 10.

The digital inputs of the DSC are the inputs of the first and second memory registers, and its analog output is the output of the bandpass filter (PF).

Digital frequency synthesizer operates as follows.

The reference generator 9 generates a sinusoidal signal of a clock frequency, from which a sequence of clock pulses of the meander shape are formed in the generation and delay unit 10, which serve to synchronize the operation of the main units of the DSC: counter, code multiplier, digital storage device and DAC.

Suppose that at time t _{0 the} code C _{i is} written in the first memory register 1, and code B _j - in the second memory register 7. Let at time t _{1 the} code C _{i is} written from the first memory register to the register of the multiplier codes multiplier, and the code B _j through the frequency counter 8 is recorded in the register of the multiplier of the code multiplier 2.

Further, starting from the second clock pulse at time instants t ₂ , t ₃ , t ₄ ... t _n, the summation result in the first digital storage device will change according to the formula:

where T is the number of the clock pulse.

In the digital storage device 3, the summation result is described by the expression:

The high-order bit of the digital storage device is an iconic SGN; it is fed to the inversion control input of the functional converter 4; the remaining bits of sin (S) through a functional converter are fed to the information input of the DAC 5, where it is converted into an analog sinusoidal signal. This signal is filtered in a bandpass filter (PF). PF has a bandwidth (see Fig. 2) from ƒ _m to ƒ _m + ƒ _c .

Then the FM signal at the output of the CSC can be described by the expression:

where U ₀ is the signal amplitude.

Thus, a digital frequency synthesizer generates a signal in the frequency band above the clock frequency, which is important for radar and communication tasks.

Literature

1. RF patent No. 2358384. IPC H03L 7/18. Digital synthesizer of frequency and phase-modulated signals / Ryabov I.V., Yuryev P.M. Claim 05/31/2007. Publ. 12/02/2008. Bull. Number 35. - 5 sec.

2. RF patent No. 2058659. MKI Н03В 19/00. Digital frequency synthesizer / Ryabov I.V., Fishchenko P.A. Claim 09/23/1993. Publ. 04/20/1996. Bull. No. 11. - 6 p. (prototype).

Claims (1)

A digital frequency synthesizer containing a series-connected reference generator and a block of formation and delay, the first and second memory registers, a binary counter, a digital storage device and a DAC ;, the output of the second memory register is connected to the input of a binary counter, the outputs of the formation and delay unit are connected to the clock inputs of a digital drive, binary counter and DAC, characterized in that the block of formation and delay is made in the form of a block of formation of clock pulses in the form of a "meander", and also introduced a code multiplier, fu National code-sine converter, bandpass filter; the output of the first memory register is connected to the first input of the code multiplier, the second input of the code multiplier is connected to the output of the binary counter, and the output of the code multiplier is connected to the input of the digital storage device, the output of the last one is connected to the input of the code-sine functional converter, its output is connected to the information input of the DAC, the outputs of the formation and delay unit are connected to the three clock inputs of the code multiplier.

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