RU2058659C1 - Digital oscillator - Google Patents

Abstract

FIELD: radar equipment. SUBSTANCE: device has clock 1, delay unit 2, first and second memory registers 3 and 11, initial-setting counter 4, first and second read-only memory units 5 and 8, digital-to-analog converter 6, low-pass filter 7, first and second accumulating registers 11 and 12. EFFECT: increased speed. 1 dwg

Description

 The invention relates to electronic equipment, is intended for the synthesis of signals with linear frequency modulation (LFM) and can be used in radar, communication systems and sounding of various media, in particular the ionosphere.

 Known digital frequency synthesizers containing two read-only memory blocks, a drive, a code multiplier, a preset counter, a 6-code converter, a memory register, a digital-to-analog converter, a low-pass filter, a clock generator, a delay unit.

 The closest technical solution to the proposed one is a digital frequency synthesizer containing a series-connected clock generator and a delay unit, a series-connected memory register, a digital-to-analog converter and a low-pass filter, a first read-only memory unit, a code multiplier, a code converter and a drive, the clock input of which is connected with the first tap of the delay unit, the second tap of which is connected to the clock input of the memory register, the second ok permanent storage and a preset counter, the clock input of which is connected to the first tap of the delay unit, the third tap of which is connected to the input of the write signal of the multiplier code multiplier, whose inputs are multiply connected to the output of the drive, the information inputs of which are connected to the outputs of the first read-only block, and the outputs of the counter with a preset are connected to the inputs of the multiplier of the codes, the output of the signal of the highest category of which is connected to the input of the signal of the senior bit the poison of the code converter, the code inputs of the signal of the least significant bits of which are connected to the code outputs of the signals of the least significant bits of the code multiplier, the outputs of the code converter are connected with the information inputs of the memory register.

 However, the known frequency synthesizers do not provide a sufficiently high speed.

 The purpose of the invention is improving performance.

 In FIG. 1 shows a structural diagram of a digital frequency synthesizer; figure 2 (a, b, c, d) diagrams of work.

 The digital frequency synthesizer contains a clock 1, a delay unit 2, a first memory register 3, a counter 4 with preset, the first read-only memory 5, a digital-to-analog converter (DAC 6), a low-pass filter 7, the second read-only memory 8, the first drive 9, code converter 10, second memory register 11, second drive 12.

 The positive effect of increased speed compared to existing frequency synthesizers is achieved by eliminating the multiplication operation and introducing an additional summing operation, and since the time of performing the summing operation is an order of magnitude shorter than the multiplication, the device’s speed increases.

где А результат суммирования;
С_i код начальной частоты;
Т номер тактового импульса;
ДК код коэффициента деления счетчика 4.Digital frequency synthesizer operates as follows. At time t _o (see Fig. 2, b), information from the second permanent storage unit 8, depending on the address at the inputs C _{i, is} recorded in the second memory register 11, at the same time, recording from the first permanent storage unit 5, depending on the address of the DC in counter with a preset 4. At time t ₁ (see Fig. 2, b), summation occurs in the second drive 12 and the result of summation is recorded in the first memory register 3. At time t ₂ (see Fig. 2, b), zeroing occurs the second memory register 11, and in the second drive 12 with each subsequent so ovym pulse t _n will occur change in the result of summation by the formula
AC _i +

where A is the result of the summation;
C _{i is} the initial frequency code;
T is the clock number;
DC code of the division ratio of the counter 4.

Старший разряд суммирования SGN является знаковым и поступает на вход управления инверсией преобразователя кодов 10. Остальные N старших разрядов (N число разрядов ЦАП 6) через преобразователь кодов 10 поступают на информационные входы ЦАП 6. Если SGN равен логическому "0", то на ЦАП поступает прямой двоичный код суммирования, если же SGM равен 1, то на ЦАП 6 поступает обратный код суммирования.At the outputs of the first drive 9, the result will change according to the formula
B = A • T = C _i • T +

The highest bit of the summation SGN is significant and goes to the inversion control input of the code converter 10. The remaining N senior bits (N is the number of bits of the DAC 6) through the code converter 10 go to the information inputs of the DAC 6. If the SGN is logical "0", then the DAC direct binary summation code, if SGM is 1, then the reverse summation code is sent to DAC 6.

Если принять, что C_i= ω_o, 1/ДК= 0,5

, T Δt, где ω_o начальная циклическая частота

скорость изменения циклической частоты, то
Φ= ω_ot + 0,5

t² Фильтр нижних частот 7 пропускает на выход цифрового синтезатора частот только первую гармонику сформированного сигнала. В результате фильтрации на выходе цифрового синтезатора частот формируется ЛЧМ-сигнал, амплитуда которого изменяется по закону:
U(t) U_m• sin(ω_ot+0,5

t²) где U_m- максимальное значение амплитуды сигнала на выходе синтезатора частот.Then, after digital-to-analog conversion, the output of the DAC 6 will be a step signal of a "triangular" shape, the phase of which changes as follows:
Φ BC _i • T +

If we assume that C _i = ω _o , 1 / DK = 0.5

, T Δt, where ω _{o is the} initial cyclic frequency

rate of change of cyclic frequency then
Φ = ω _o t + 0.5

t ² Low-pass filter 7 passes only the first harmonic of the generated signal to the output of the digital frequency synthesizer. As a result of filtering, an LFM signal is generated at the output of the digital frequency synthesizer, the amplitude of which changes according to the law:
U (t) U _m • sin (ω _o t + 0.5

t ² ) where U _m is the maximum value of the signal amplitude at the output of the frequency synthesizer.

 The clock generator 1 with delay unit 2 starts and synchronizes all nodes of the digital synthesizer.

< 2 где f_конечн конечная частота;
f_нач начальная частота.The counter with preset 4 is used as a divider with a variable division ratio. Depending on the DK code, the rate of change of the frequency of the digital frequency synthesizer will change. A digital frequency synthesizer allows you to synthesize FM signals with large bases. It is advisable to use it so that the following condition is met:

<2 where f _{is a} finite finite frequency;
f _nach initial frequency.

Claims (1)

 A DIGITAL FREQUENCY SYNTHESIZER, comprising a series-connected clock generator and a delay unit, a series-connected digital-to-analog converter and a low-pass filter, a counter with preset, the first memory register, the first and second read-only memory blocks, the first drive and code converter, while the installation input of the first the memory register is connected to the first output of the delay unit, the second output of which is connected to the counting input of the counter with a preset, the inputs of which are connected to the corresponding outputs of the first permanent memory unit, the inputs of the first and second permanent memory units and the output of the low-pass filter are respectively the first and second inputs and output of a digital frequency synthesizer, characterized in that a second memory register and a second drive are connected in series the outputs of which are connected to the corresponding code inputs of the first memory register, the outputs of which are connected to the corresponding code inputs of the first memory an amplifier, while the outputs of the second read-only memory unit are connected to the corresponding code inputs of the second memory register, the installation input of which is connected to the third output of the delay unit, the counter output with preset is connected to the counting input of the second drive, the information outputs of the first drive are connected to the corresponding information inputs of the converter codes, the outputs of which are connected to the corresponding code inputs of the digital-to-analog converter, and the signal output of the highest signal the first discharge of the first drive is connected to the input control inversion of the code Converter.

Images