RU2634190C1 - Interference rejecting counter - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: interference rejecting counter comprises: the first, the second and the third delay units, a weight unit, the first and the second complex multipliers, a weight unit, a complex adder, a sync generator, a complex conjugation unit, a switching unit, an accuracy unit, a switching unit and a two-channel switch.

EFFECT: increasing the signal extraction efficiency of moving targets.

11 dwg

Description

The invention relates to computer technology and can be used in coherent-pulse radar systems to isolate the signals of moving targets against a background of passive interference during group tuning of the carrier frequency of the probe pulses.

Known radar device for detecting a moving target [1], containing sequentially included delay blocks, a complex number multiplier and a subtractor. However, this device has a low signal extraction efficiency for a moving target.

Another known device is the correlation auto-compensator [2], which contains a number of delay units, two multipliers, an adder and a unit for estimating the parameters of the correlated noise. The disadvantage of this device is the poor suppression of the edges of the extended interference due to the large time constant of the adaptive feedback circuit.

Closest to the present invention, a digital device for suppressing passive interference [3], selected as a prototype, contains two delay blocks, a block of weight coefficients, two complex multipliers, a weight block and a complex adder. However, this device due to the transient process upon receipt of the edge of the passive interference has a low efficiency of signal extraction of moving targets.

The problem to be solved in the invention is to increase the efficiency of rejecting passive interference and isolating signals of moving targets when processing a group of pulses against a background of passive interference with an a priori unknown Doppler speed.

To solve this problem, a calculator for noise suppression, containing the first and second delay blocks, a weight coefficient block, the first and second complex multipliers, a weight block and a complex adder, introduces a complex conjugation block, a switching block, an accuracy block, a switching block, a two-channel switch, and sync generator.

Additional blocks introduced into the proposed device are known. Thus, the first delay unit, the first complex multiplier, the weight unit, and the complex adder connected together are used for rejecting passive interference, but their application together with the switching unit and two-channel switch is not known for more accurate interference compensation. New are the links between the weighting unit and the switching unit and the weight unit, the accuracy unit and the second complex multiplier, the second delay unit, a two-channel switch, the second complex multiplier and the switching unit, as well as the connections between the clock generator and the rest of the calculator blocks, which suppress, accordingly, the optimal and consistent processing of the group of pulses, which, combined with more accurate interference compensation, leads to an increase in the efficiency of extraction with ignals of moving targets during carrier frequency tuning against a background of passive interference with an a priori unknown Doppler speed.

Comparison with technical solutions known from published sources of information shows that the claimed solution has novelty and has an inventive step.

The claimed solution is technical in nature, feasible, reproducible and, therefore, is industrially applicable.

In FIG. 1 shows a block diagram of a calculator for suppressing interference; in FIG. 2 - delay unit; in FIG. 3 - block complex conjugation; in FIG. 4 - complex multiplier; in FIG. 5 - weight block; in FIG. 6 - complex adder; in FIG. 7 - switching unit; in FIG. 8 - precision block; in FIG. 9 - drive; in FIG. 10 - unit calculation module; in FIG. 11 - two-channel switch.

The computer for suppressing interference (Fig. 1) contains a first delay unit 1, a weighting unit 2, a first complex multiplier 3, a weight unit 4, a complex adder 5, a second complex multiplier 6, a switching unit 7, a second delay unit 8, an integrated unit 9 pairing, block 10 switching, block 11 precision, two-channel switch 12 and a clock 13.

Block 1 delay (Fig. 2) contains two random access memory 14; block 9 complex interface (Fig. 3) contains an inverter 15; complex multiplier 3, 6 (Fig. 4) contains two channels (I, II), each of which contains multipliers 16, 17 and the adder 18; the weight unit 4 (Fig. 5) contains two multipliers 19; complex adder 5 (Fig. 6) contains two adders 20; block 10 switching (Fig. 7) contains a counter 21, a decoder 22, blocks 23 matches and the adder 24; block 11 accuracy (Fig. 8) contains a drive 25, block 26 calculating the module and two divider 27; drive 25 (Fig. 9) contains two channels (I, II), consisting of n delay elements 28 for the interval t _d and n adders 29; unit 26 computing module (Fig. 10) contains two multipliers 30, adder 31 and block 32 extract the square root; two-channel switch 12 (Fig. 11) contains two switches 33.

The calculator for suppressing interference works as follows.

A group of coherent radio pulses, initially radiated with the same carrier frequency and consisting of a signal from a moving target and passive interference significantly exceeding the signal, is fed to the input of a receiving device, in which it is amplified, is transferred to the video frequency in quadrature phase detectors, and then subjected to analog-to-digital conversion (corresponding blocks in Fig. 1 are not shown).

The digital codes (x _kl , y _kl ) of both quadrature projections following through the repetition period T in each range resolution element (range ring) of each repetition period form a sequence of complex numbers

,

,

, здесь

- доплеровская частота помехи.where k is the number of the current period, l is the number of the current range ring, ϕ _l is the Doppler shift for the phase repetition period (usually interference, due to its significant excess over the signal), equal

, here

- Doppler interference frequency.

Digital readings in the inventive device (Fig. 1) are supplied to the inputs of the first delay unit 1 (Fig. 2) and to the inputs of the weight unit 4 connected to them (Fig. 5). Each of the delay blocks 1, 8 (Fig. 2) consists of parallel-connected random access memory (RAM) 14. Moreover, each RAM 14 serves to store the values of the samples from the range rings of each quadrature channel for one period.

In block 9 of complex conjugation using an inverter 15 (Fig. 3), the sign of the imaginary projections of the delayed samples is inverted. In the complex multiplier 3, the multiplication of the corresponding complex numbers occurs, realized by operations with the projections of these numbers in accordance with FIG. 4. Formed values

с n+1 смежных элементов разрешения по дальности временного строба, кроме элемента с номером n/2+1, для чего выходные величины элемента 28 задержки с номером n/2 поступают только на последующий элемент 28 задержки (фиг. 9). На выходах накопителя 25 (фиг. 9) образуются величиныenter the accuracy block 11 (Fig. 8), in which the drive 25 (Fig. 9), using the delay elements 28 and the adders 29, sums the works sliding along the range in each repetition period

from n + 1 adjacent resolution elements in the range of the time strobe, except for the element with the number n / 2 + 1, for which the output values of the delay element 28 with the number n / 2 go only to the subsequent delay element 28 (Fig. 9). At the outputs of the drive 25 (Fig. 9) values are formed

- оценка сдвига фазы помехи за период повторения, усредненная по n смежным элементам разрешения по дальности.Where

- an estimate of the phase shift of the interference over the repetition period averaged over n adjacent range resolution elements.

, поступающие на первые входы комплексного перемножителя 6. Точность определения величины

определяется числом накапливаемых отсчетов n.In block 26, the calculation of the module (Fig. 10) determines the values | Y _k |, and then at the outputs of the dividers 27 (Fig. 8) - values

entering the first inputs of the complex multiplier 6. Accuracy of determining the value

determined by the number of accumulated samples n.

In the weight unit 4 (Fig. 5), the incoming samples are weighed by the weighting factors g _k , which are stored in the weighting unit 2. The number of weight coefficients g _k is determined by the implemented order of the calculator m associated with the number of pulses in the group equal to m + 1. In particular, when m = 1, the weighting coefficients g ₀ = -g ₁ = 1; when m = 2-g ₀ = g ₂ = 1, g ₁ = -2; with m = 3-g ₀ = -g ₃ = 1, g ₂ = -g ₃ = -3. The weights are switched in each repetition period by the switching unit 10 (Fig. 7), which provides the processing of a group of pulses (samples) with the same initial carrier frequency.

The pulse from the radar synchronizer (not shown in Fig. 1), corresponding to the radiation of the probe pulse in each period, is fed to the first control input (1) of the calculator (Fig. 1), which is the first control input (1) of the switching unit 10, and then to counting input of the counter 21 (Fig. 7). The counter readings corresponding to the pulse number in the group in the decoder 22 are converted into a single signal at the output pulse of the decoder 22 corresponding to the pulse number. This signal opens the coincidence cascade 23 connected to it, through which the corresponding weight coefficient passes through the adder 24 to the output of the switching unit 10 . Thus, each period and, therefore, each impulse in the group has its own weight coefficient.

весовыми суммами отсчетов всех предыдущих импульсов группы. В конечном счете, в результате весовой обработки отсчетов m+1 периодов образуется величинаThe samples weighted in the weight unit 4 are summed in the complex adder 5 with the delays delayed in the second block 8 for the repetition period T, passed through the two-channel switch 12 and multiplied in the second complex multiplier 6 by the amount

weighted sums of samples of all previous pulses of the group. Ultimately, as a result of weight processing of samples of m + 1 periods, the value

.

.

обеспечивает синфазность суммируемых отсчетов, а их взвешивание коэффициентами g_k - подавление (компенсацию) слагаемых отсчетов помехи. Сигнал от движущейся цели из-за сохранения доплеровских сдвигов фазы не подавляется.Two-dimensional rotation of delayed samples at an angle

provides the common mode of the summed samples, and their weighing by the coefficients g _k - suppression (compensation) of the summands of the interference samples. The signal from a moving target due to the conservation of Doppler phase shifts is not suppressed.

The delay time of the phase shifts introduced in the second complex multiplier 6 ensures their correspondence to the middle element of the training sample, excluded in the drive 25 (Fig. 9) in accordance with expression (1). Then, in the case of a signal commensurate in magnitude with the interference, or discontinuous interference when suppressing the interference samples from the resolution element containing the signal, the possibility of attenuation or suppression of the signal due to its effect on the estimates used is excluded.

After the processing of data of m + 1 periods and the next tuning of the carrier frequency to the second control inputs (2) of the device (Fig. 1) and the switching unit 10 (Fig. 7) and the control input of the switching unit 7, a pulse arrives that resets the counter 21, and in block 7 switching switches the relaxation generator (multivibrator). At the command of the switching unit 7, the two-channel switch 12 switches the second delay unit 8 to the output of the calculator, and during the repetition period T, the results of the notch V are read. The data of the first period of the next group are received and processed at the input of the calculator to suppress interference.

дискретизации t_д, выбираемому из условия требуемой разрешающей способности по дальности.The synchronization of the computer for suppressing interference is carried out by applying to all the blocks of the claimed device a sequence of synchronizing pulses from the sync generator 13 (Fig. 1), controlled together with the pulser 10 switching pulses (l) of the radar synchronizer (not shown in Fig. 1), with an interval T. The repetition period of the synchronizing pulses is equal to the interval

discretization t _d selected from the conditions of the required resolution in range.

The technical result achieved is as follows. The output device does not receive uncompensated residual interference in the transition mode, traditionally masking the signal from the target. In the proposed device, the output receives only compensated residual noise in the steady state, which eliminates the effect of the "edge" of the noise and increases the efficiency of signal extraction of moving targets.

Thus, a computer for suppressing interference increases the efficiency of compensating for interference and isolating the signals of moving targets against the background of passive interference with an a priori unknown Doppler speed.

Bibliography

1. Patent No. 63-49193 (Japan), IPC G01S 13/52. Radar device for detecting a moving target / K.K. Toshiba. Publ. 10/03/1988. - Inventions of the countries of the world. - 1989. - Issue 109. - No. 15. - S. 52.

2. Radio-electronic systems: fundamentals of construction and theory. Reference book / Ya.D. Shirman, S.T. Baghdasaryan, A.S. Malyarenko, D.I. Lekhovitsky [et al.]; edited by Y.D. Shirman. - 2nd ed., Revised. and add. - M .: Radio engineering, 2007; from. 439, fig. 25.22.

3. A.S. 743208 USSR, IPC G01S 7/36. Digital device for suppressing passive interference / D.I. Popov. - No. 2540079/09; declared 11/03/1977; publ. 06/25/1980, Bull. Number 23. - 4 p.

Claims (1)

A computer for suppressing interference, comprising a first delay unit, a weighting unit, a first complex multiplier, a weight unit, a complex adder, a second complex multiplier and a second delay unit, wherein the inputs of the first delay unit are connected to the first inputs of the first complex multiplier and the first inputs of the weight unit the outputs of which are connected to the first inputs of the complex adder, the second inputs of which are connected to the outputs of the second complex multiplier, characterized in that complex interface, a switching unit, an accuracy unit, a switching unit, a two-channel switch and a clock generator, while the outputs of the first delay unit are connected to the inputs of the complex interface unit, the outputs of which are connected to the second inputs of the first complex multiplier, the outputs of which are connected to the inputs of the precision unit, the outputs of which connected to the first inputs of the second complex multiplier, the outputs of the weighting unit are connected to the main inputs of the switching unit, the output of which is connected to by the input of the weighing unit, the first control input of the switching unit is connected to the first control input of the calculator for noise rejection, the outputs of the complex adder are connected to the inputs of the second delay unit, the outputs of which are connected to the main inputs of the two-channel switch, the first outputs of which are connected to the second inputs of the second complex multiplier, and the control input is with the output of the switching unit, the second control input of the switching unit and the control input of the switching unit are connected to the second control the input of the computer for rejection interference, the control input of the clock is connected to the first control input of the computer for noise rejection, and the output of the clock is connected to the sync inputs of the first delay unit, the block of weight coefficients, the first complex multiplier, weight block, complex adder, the second complex multiplier, the second block delays, complex conjugation unit, switching unit, accuracy unit, switching unit and two-channel switch, the main inputs of the subtracting a suppressor for suppressing interference are the connected inputs of the first delay unit and the weight unit, and the outputs are the second outputs of the two-channel switch.

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