RU2560130C1 - Pulsed radio signal detection and measurement device - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: pulsed radio signal detection and measurement device includes a delay unit, a complex conjugation unit, a complex multiplication unit, an averaging unit, a phase computation unit, a multiplier, a switch, a magnitude computation unit, a first memory unit, a control unit, a threshold unit, a second memory unit, a clock generator, first and second double-channel switches, an additional averaging unit, an additional delay unit, an additional magnitude computation unit, an additional complex conjugation unit, an additional complex multiplication unit and an adder, which perform inter-period correlation processing of initial readings.

EFFECT: high accuracy of measuring velocity and wider range of uniquely measured Doppler velocities while maintaining unique range measurement.

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Description

The invention relates to computer technology and is intended for calculation based on the correlation principle of the speed of a moving object; can be used in automated air traffic control systems to detect and measure the speed of aircraft.

Known multi-channel non-tracking filter meter [1], each channel of which contains a matched filter and detector connected in series, the outputs of the channels are combined by a resolver. However, this device has a low measurement accuracy, as well as the complexity of the implementation of multi-channel processing.

A device for processing a signal of a moving target [2] is also known, which contains series-delayed blocks, a complex number multiplier, and a subtractor. However, this device has low accuracy and ambiguity of measurement.

Closest to the invention is a Doppler signal detector-meter [3], selected as a prototype, comprising a delay unit, a complex conjugation unit, a complex multiplication unit, an averaging unit, a phase calculation unit, a multiplier, a key, a module calculation unit, a first memory unit, a control unit, a threshold unit, a second memory unit and a clock generator, while the outputs of the delay unit are connected to the inputs of the complex conjugation unit, the outputs of which are connected to the first inputs of the complex multiplication unit, the second the inputs of which are combined with the inputs of the delay unit, which are the inputs of the detector-meter, the outputs of the complex multiplication unit are connected to the inputs of the averaging unit, the outputs of which are connected to the inputs of the module calculation unit and the inputs of the phase calculation unit, the output of the module calculation unit is connected to the second input of the threshold block, the first the input of which is connected to the second memory block, the control input of the key is connected to the output of the threshold block, which is the first output of the detector-meter, the second output of which is the output of the multiplier, the first and second inputs of which are respectively connected to the output of the first memory block and the output of the key. However, this device has ambiguity and low measurement accuracy due to the presence of a large number of functional transformations associated with signal processing using wobble of the repetition period.

The problem to be solved in the invention is to expand the range of unambiguously measured radial velocities and increase the accuracy of the measurement due to the smaller number of functional transformations when using joint processing of non-equidistant radio-pulse signals.

To solve the problem, a device for detecting and measuring radio pulse signals, comprising a delay unit, a complex conjugation unit, a complex multiplication unit, an averaging unit, a phase calculation unit, a multiplier, a key, a first memory unit, a module calculation unit, a control unit, a threshold unit, and a second a memory unit and a clock generator, the first and second two-channel keys, an additional averaging unit, an additional delay unit, an additional module calculation unit, an additional complex conjugation unit are introduced , An additional block of complex multiplication and an adder.

Additional blocks introduced into the proposed device are known. Thus, the delay unit, the complex conjugation unit, and the complex multiplication unit connected together allow one to isolate the Doppler phase incursion for the interval between adjacent pulses. However, the joint use of the delay unit, complex conjugation unit, complex multiplication unit, first and second two-channel keys, control unit, additional delay unit, additional complex conjugation unit, additional complex multiplication unit, additional module calculator, and adder is not known. The connections of the first and second two-channel keys with the complex multiplication unit and the control unit, the averaging unit with the first two-channel key and the additional delay unit, the additional averaging unit with the second two-channel key and the additional complex conjugation unit, the additional complex multiplication unit with the additional delay unit and the additional are new complex conjugation unit, an additional complex multiplication unit with a phase calculation unit and an adder with a calculation unit module, an additional unit for calculating the module and the threshold unit, which provides an extension of the range of unambiguously measured radial velocities and an increase in measurement accuracy due to a smaller number of functional transformations when using joint processing of radio-pulse signals. Communications between the sync generator and all blocks of the device for detecting and measuring radio pulse signals provide consistent processing of a non-equidistant sequence of radio pulses.

Comparison with the technical characteristics known from published sources of information shows that the claimed solution has novelty and has an inventive step.

The claimed solution is technical in nature, feasible, reproducible and, therefore, is industrially applicable.

In FIG. 1 is a structural electrical diagram of a device for detecting and measuring radio pulse signals; in FIG. 2 - delay unit; in FIG. 3 - block complex conjugation; in FIG. 4 - block complex multiplication; in FIG. 5 - averaging unit; in FIG. 6 - phase calculation unit; in FIG. 7 - character assignment unit; in FIG. 8 - module calculation unit, in FIG. 9 - a two-channel key; in FIG. 10 - control unit.

The device for detecting and measuring radio pulse signals (Fig. 1) contains a delay unit 1, complex conjugation unit 2, complex multiplication unit 3, averaging unit 4, phase calculation unit 5, multiplier 6, key 7, module calculation unit 8, first memory unit 9 , control unit 10, threshold block 11, second memory unit 12, sync generator 13, first two-channel key 14, second two-channel key 15, additional averaging unit 16, additional delay unit 17, additional module calculation unit 18, additional complex conjugation unit 19 an additional complex multiplication unit 20 and an adder 21, wherein the outputs of the delay unit 1 are connected to the inputs of the complex conjugation unit 2, the outputs of which are connected to the first inputs of the complex multiplication unit 3, the second inputs of which are combined with the inputs of the delay unit 1, the output of the first block 9 the memory is connected to the first input of the multiplier 6, the output of which is connected to the input of the key 7, the output of the threshold block 11 is connected to the control input of the key 7, the first input of the threshold block 11 is connected to the output of the second memory block 12, the outputs of block 3 complex multiplication connected to the combined inputs of the first 14 and second 15 two-channel keys, the control inputs of which are connected respectively to the first and second outputs of the control unit 10, the outputs of the first two-channel key 14 are connected to the inputs of the averaging unit 4, the outputs of which are connected to the inputs of the additional delay unit 17, the outputs of the second two-channel key 15 are connected to the inputs of the additional averaging unit 16, the outputs of which are connected to the combined inputs of the additional module calculation unit 18 and additional of the additional complex interface unit 19, the outputs of the additional delay unit 17 are connected to the combined inputs of the module calculation unit 8 and the first inputs of the additional complex multiplication unit 20, the second inputs of which are connected to the outputs of the additional complex interface unit 19, the outputs of the module calculation unit 8 and the additional calculation unit 18 modules are connected respectively to the first and second inputs of the adder 21, the output of which is connected to the second input of the threshold unit 11, the outputs of the additional unit 20 to multiplex multiplication is connected to the inputs of the phase calculation unit 5, the output of which is connected to the second input of the multiplier 6, the output of the clock generator 13 is connected to the clock inputs of the delay unit 1, complex conjugation unit 2, complex multiplication unit 3, averaging unit 4, phase calculation unit 5, multiplier 6 , key 7, module calculation unit 8, first memory block 9, threshold block 11, second memory block 12, first 14 and second 15 two-channel keys, additional averaging block 16, additional delay block 17, additional block and 18, the calculation of the module, the additional complex conjugation block 19, the additional complex multiplication block 20, and the adder 21, the inputs of the detection and measurement of radio pulse signals are the inputs of the delay unit 1, and the first and second outputs are the outputs of the key 7 and the threshold block 11, respectively.

The delay unit 1 and the additional delay unit 17 (Fig. 2) contain two digital delay lines 22, the inputs of the delay units are the inputs of the digital delay lines 22, the outputs of which are the outputs of the delay units.

The complex conjugation unit 2 and the additional complex conjugation unit 19 (Fig. 3) comprise an inverter 23, the first input of the complex conjugation block is its first output, the second input is the inverter input, the output of which is the second output of the complex conjugation block.

The complex multiplication block 3 and the additional complex multiplication block 20 (Fig. 4) contain two channels (I, II), each of which includes a first multiplier 24, a second multiplier 25 in series, and an adder 26, the output of the first multiplier 24 of one channel is connected to the second the input of the adder 26 of the other channel, and the first and second inputs of the complex multiplication block, respectively, are the combined first inputs of the first and second multipliers 24, 25 of each channel, the combined second inputs of the first Ithel 24 and the combined second inputs of the second multipliers 25 and the output unit are complex multiplication outputs of adders 26 of each of the channels.

Block 4 averaging and additional block 16 averaging (Fig. 5) contain two channels (I, II), each of which consists of (N-3) / 2 series-connected digital delay lines 27 and (N-3) / 2 series-connected adders 28, the inputs of the averaging block are the combined inputs of the first delay line 27 and the first adder 28 of each channel (I, II), and the output of the k-th [k = 1 ... (N-3) / 2] delay line 27 is connected to the second input of the kth [k = 1 ... (N-3) / 2)] adder 28 of each channel (I, II), the outputs of the averaging block are the outputs of the [(N-3) / 2] -x adders 28.

The phase calculation unit 5 (Fig. 6) consists of a series divider 29, a functional converter 30, a modular block 31, an adder 32, a character assignment unit 33 and a first key 34, the output of the functional converter 30 is connected to the input of the second key 35, the second input of the adder 32 is connected to the output of the memory unit 37, the control inputs of the first and second keys 34, 35 are connected to the input of the divider 29 corresponding to the input of the real part of the complex number, the second input of the character assignment unit 33 is connected to the input of the divider 29, corresponding For the input of the imaginary part of the complex number, the outputs of the first and second keys 34, 35 are connected to the inputs of the adder 36, the output of which is the output of the phase calculation unit, the inputs of the phase calculation unit are the inputs of the divider 29.

The character assigning unit 33 (Fig. 7) contains multiplication units 38, 41, a memory unit 39 and a limiter 40, the second input of the character assigning unit being the first input of the multiplying unit 38, the second input of which is connected to the output of the memory unit 39, the output of the multiplying unit 38 connected to the input of the limiter 40, the output of which is connected to the first input of the multiplication unit 41, the second input of which is the first input of the character assignment unit, the output of the character assignment unit is the output of the multiplication unit 41.

The module calculation unit 8 and the additional module calculation unit 18 (Fig. 8) contain two multiplication units 42, an adder 43 and a square root extraction unit 44, the inputs of the module calculation unit are the inputs of the multiplication units 42, the outputs of which are connected to the first and second inputs of the adder 43 whose output is connected to the input of the square root extraction unit 44, the output of which is the output of the module calculation unit.

The first 14 and second 15 two-channel keys (Fig. 9) contain two keys 45, the inputs of the two-channel keys are the inputs of the keys 45, the outputs of which are the outputs of the two-channel keys.

The control unit 10 (Fig. 10) contains a trigger 46 and an element HE 47, the input of the control unit is the input of the trigger 46, the output of which is connected to the input of the element HE 47, the first output of the control unit 10 is the output of the trigger 46, and the second output is the output of the element NOT 47.

A device for detecting and measuring radio pulse signals operates as follows.

In the inventive detection-measurement device, a non-equidistant coherent-pulse sequence of N radio pulses with alternating repetition periods T ₁ and T _{2 is} processed, with T ₁ -T ₂ = ΔT. When radio pulses are reflected from a moving target, their carrier frequencies in the corresponding periods acquire Doppler phase shifts

φ ₁ = 2πf _d T ₁ , φ ₂ = 2πf _d T ₂ , Δφ = φ ₁ -φ ₂ = 2πf _d ΔT,

where f _d = 2v _r f _n / s is the Doppler frequency, v _r is the radial velocity of the target, f _n is the carrier frequency of the radio pulses, and s is the propagation velocity of radio waves.

The radio pulses reflected from the target arrive at the input of the receiver, in which they are amplified, are transferred to the video frequency in quadrature phase detectors, and then undergo analog-to-digital conversion (the corresponding blocks in Fig. 1 are not shown). At the input of the detection-measurement device in one element of range resolution, digital samples of the complex envelope are received

U _k = u _1k + iu _2k , k = 1 ... N,

where u _1k , u _2k are the digital codes of the real and imaginary parts of the samples U _k .

. Далее в блоке 3 комплексного умножения (фиг. 4) реализуется попарное умножение отсчетов в соответствии с алгоритмомThe input samples U _{k of} the detection-measurement device (Fig. 1) in the delay unit 1 (Fig. 2) under the control of the synchronizing pulses generated by the sync generator 13 are alternately delayed by the intervals T ₁ and T ₂ , which ensures synchronization of the subsequent complex multiplication of the samples in range . The sync generator 13 is controlled by the pulses of the radar synchronizer (not shown in Fig. 1), following alternately at intervals T ₁ and T ₂ . In block 2 complex pairing (Fig. 3) is a complex pairing of the delayed reference $$(U_{k-\mathrm{one}}^{*})$$

. Further, in block 3 of complex multiplication (Fig. 4), pairwise multiplication of samples is implemented in accordance with the algorithm

раздельно для каждого интервала T₁ и Т₂ соответственно через первый 14 и второй 15 двухканальные ключи раздельно поступают в блок 4 усреднения и в дополнительный блок 16 усреднения (фиг. 5). Поочередная коммутация первого 14 и второго 15 двухканального ключей осуществляется импульсами соответственно с первого и второго выходов блока 10 управления, синхронизируемого также импульсами синхронизатора радиолокатора.Pairwise products (correlations) $$(U_{k-\mathrm{one}}^{*}{U}_k)$$

separately for each interval T ₁ and T _2, respectively, through the first 14 and second 15 two-channel keys are separately received in block 4 averaging and in an additional block 16 averaging (Fig. 5). Alternate switching of the first 14 and second 15 two-channel keys is carried out by pulses, respectively, from the first and second outputs of the control unit 10, synchronized also by the pulses of the radar synchronizer.

In block 4 averaging (Fig. 5), using delay lines 27 for the interval T ₁ + T ₂ and adders 28 in each range resolution element, coherent summation (accumulation) _of pairwise products (correlations) corresponding to the interval T _{1 is} performed along the azimuth. As a result, at the output of block averaging 4 for odd N, a value proportional to the correlation moment of samples corresponding to the interval T _{1 is formed} , the quantity

In the additional averaging block 16 (Fig. 5), a similar summation _of pairwise correlations corresponding to the T ₂ interval is performed, which leads to the formation at its output proportional to the correlation moment of the samples corresponding to the T ₂ interval,

The value of Y ₁ at the output of the averaging unit 4 (Fig. 5) in time precedes the value of Y ₂ by the interval T ₂ , which is compensated by the corresponding delay Y ₁ in the additional delay unit 17 (Fig. 2). In the additional block 19 complex conjugation (Fig. 3) the sign of the imaginary part of the value Y _{2 is} inverted.

одновременно поступают соответственно на первые и вторые входы дополнительного блока 20 комплексного умножения (фиг. 4), на выходе которого вычисляется величинаValues Y ₁ and $${\mathrm{<figure-callout\; id="2"\; label="Y"\; filenames="00000017.png,00000019.png"\; state="\{\{state\}\}">Y</figure-callout>}}_2^{*}$$

simultaneously arrive, respectively, at the first and second inputs of the additional complex multiplication unit 20 (Fig. 4), at the output of which the value is calculated

The values of v ₁ and v ₂ are supplied to the corresponding inputs of the phase calculation unit 5 (Fig. 6), where, based on the division unit 29 and the arc tangent functional converter 30, an estimate is calculated

зависят от знака величины v₁. При v₁>0 открыт второй ключ 35, и оценка

через сумматор 36 непосредственно поступает на выход блока 5 вычисления фазы. При v₁<0 открыт первый ключ 34, а второй ключ 35 закрыт. При этом в модульном блоке 31 образуется |argV|, вычитаемый в сумматоре 32 из величины π, поступающей от блока 37 памяти. Полученной разности в блоке 33 присваивается знак величины v₂.Subsequent Assessment Conversions

depend on the sign of the quantity v ₁ . For v ₁ > 0, the second key 35 is open, and the estimate

through the adder 36 directly goes to the output of the phase calculation unit 5. When v ₁ <0, the first key 34 is open, and the second key 35 is closed. In this case, | argV | is formed in the modular block 31, which is subtracted in the adder 32 from the value of π coming from the memory block 37. The resulting difference in block 33 is assigned the sign of the value of v ₂ .

Block 33 character assignment (Fig. 7) operates as follows. The second input of the character assignment unit receives the value v ₂ , where in the multiplication unit 38 it is multiplied by a constant factor from the memory unit 39 in order to scale and further limit the limiter 40 to a level of ± 1. Thus, after the restriction, the value at the output of the limiter 40 has the meaning of a sign of the quantity v ₂ , which, entering the first input of the multiplication unit 41, is assigned the difference π- | argV | coming from the output of the adder 32 to the first input of the character assigning unit 33, i.e. e. to the second input of the multiplication block 41.

The operations considered allow, in block 5 of the phase calculation, first to find an estimate of the Doppler phase shift located in the interval [-π / 2, π / 2], and then, using subsequent logical transformations in blocks 31, 32 and 33, expand the limits of its unambiguous measurement to the interval [-π, π] according to the algorithm

на коэффициент а, хранящийся в первом блоке 9 памяти, что позволяет найти однозначную оценку радиальной скорости в соответствии с выражениемThe multiplier 6 (Fig. 1) multiplies the found phase shift estimate

by a coefficient a stored in the first memory block 9, which allows one to find an unambiguous estimate of the radial velocity in accordance with the expression

- весовой коэффициент.Where $$a=\frac{c}{\mathrm{four}\pi f_n\Delta T}$$

- weight coefficient.

To reduce the likelihood of the device working by noise, it excludes the issuance of the obtained estimate for output in the absence of a signal reflected from the target. In block 8, the calculation of the module and in the additional block 18 of the calculation of the module (Fig. 8) are calculated respectively

which go respectively to the first and second inputs of the adder 21. From the output of the adder 21, the quantity z = | Y ₁ | + | Y ₂ | arrives at the second input of the threshold block 11, in which it is compared with the threshold level z ₀ recorded in the second memory block 12. If the threshold level z ₀ is exceeded, then the output of the threshold unit 11 receives a permission signal for passing the calculation result from the output of the multiplier 6 through the key 7 to the first output of the detection and measurement device for radio-pulse signals. Otherwise, key 7 is open. In addition, the signal from the output of the threshold block 11, which is the second output of the device for detecting and measuring radio pulse signals, can be used to read other coordinates of the target, for example, range.

The synchronization device for detecting and measuring radio pulse signals is carried out by applying to all the blocks of the claimed device a sequence of synchronizing pulses generated by the synchronizer 13 (Fig. 1) with a repetition period t _k determined from the condition of the required resolution in range.

In the known device (prototype), the initial Doppler phase shifts φ ₁ and φ ₂ , by which the value Δφ = φ ₁ -φ _{2 is} calculated, have an unambiguous measurement interval [-π, π], which corresponds to an unambiguous measurement interval of the Doppler frequency [-1 / 2T ₁ , 1 / 2T ₁ ] (the largest period T ₁ ). In the proposed device, the value Δφ is measured directly, which corresponds to the interval of uniqueness of the Doppler frequencies [-1 / 2ΔТ, 1 / 2ΔТ]. Moreover, the interval of unambiguous measurement of the Doppler frequency and, consequently, the radial velocity expands by T ₁ / ΔT times, which corresponds to the solution of the problem of the invention. If, in accordance with the condition f _d ≤1 / 2ΔT and taking into account f _d = 2v _r f _n / s for the maximum possible target speed v _{rmax, we} choose the interval ΔT≤s / 4v _rmax f _n , then in the whole range of real target speeds their unambiguous measurement is carried out. This preserves the uniqueness of the range measurement, which is ensured by the appropriate choice of a shorter pulse repetition period T ₂ .

такое удвоение отсутствует, что соответствует повышению точности измерения доплеровского сдвига фазы и, следовательно, радиальной скорости цели.The errors of the separate calculation of the values of φ ₁ and φ ₂ in the known device (prototype) due to functional transformations are statistically independent. As a result, the error (dispersion) of the difference φ ₁ -φ ₂ = Δφ is doubled. In the proposed device for the direct calculation of the assessment

such a doubling is absent, which corresponds to an increase in the accuracy of measuring the Doppler phase shift and, therefore, the radial velocity of the target.

Thus, the device for detecting and measuring radio pulse signals allows you to expand the range of unambiguously measured radial velocities and improve the accuracy of speed measurements due to fewer functional transformations when using the proposed joint processing of nonequidistant radio pulse signals.

Bibliography

1. Shirman Y.D. and Manzhos V.N. The theory and technique of processing radar information against the background of interference. - M .: Radio and communication. - 1981. - S. 204. - Fig. 14.2.

2. Patent No. 63-49193 (Japan), IPC G01S 13/52. Radar device for detecting a moving target / K.K. Toshiba. Publ. 10/03/1988. - Inventions of the countries of the world. - 1989. - Issue 109. - No. 15. - S. 52.

3. Patent No. 2017167 (Russia), IPC G01S 13/58. Detector-meter of Doppler signals / D.I. Popov, S.V. Gerasimov and E.N. Mataev. Publ. 07/30/1994. - Inventions. - 1994. - No. 14. - S. 121.

Claims (1)

A device for detecting and measuring radio pulse signals, comprising a delay unit, a complex conjugation unit, a complex multiplication unit, an averaging unit, a phase calculation unit, a multiplier, a key, a module calculation unit, a first memory unit, a control unit, a threshold unit, a second memory unit, and a clock generator, the outputs of the delay unit are connected to the inputs of the complex conjugation unit, the outputs of which are connected to the first inputs of the complex multiplication unit, the second inputs of which are combined with the inputs of the delay unit, the output of of the memory block is connected to the first input of the multiplier, the output of which is connected to the key input, the output of the threshold block is connected to the control input of the key, the first input of the threshold block is connected to the output of the second memory block, the output of the clock generator is connected to the sync inputs of the delay block, complex pairing unit, complex block multiplication, averaging block, phase calculation block, multiplier, key, module calculation block, first and second memory blocks and threshold block, characterized in that the first and second two-channel are introduced keys, an additional averaging unit, an additional delay unit, an additional module calculation unit, an additional complex conjugation unit, an additional complex multiplication unit and an adder, while the outputs of the complex multiplication unit are connected to the combined inputs of the first and second two-channel keys, the control inputs of which are connected respectively to the first and second outputs of the control unit, the outputs of the first two-channel key are connected to the inputs of the averaging unit, the outputs of which are connected to the inputs and an additional delay unit, the outputs of the second two-channel key are connected to the inputs of the additional averaging unit, the outputs of which are connected to the combined inputs of the additional module calculation unit and the additional complex conjugation unit, the outputs of the additional delay unit are connected to the combined inputs of the module calculation unit and the first inputs of the additional complex multiplication unit , the second inputs of which are connected to the outputs of the additional unit complex conjugation, the outputs of the block The module and the additional module calculation block are connected respectively to the first and second inputs of the adder, the output of which is connected to the second input of the threshold block, the outputs of the additional complex multiplication block are connected to the inputs of the phase calculation block, the output of which is connected to the second input of the multiplier, the output of the clock generator is connected to the sync inputs first and second two-channel keys, additional averaging block, additional delay block, additional module calculation block, additional b a complex interface, an additional complex multiplication unit and an adder, the inputs of the device for detecting and measuring radio pulse signals are the inputs of the delay unit, and the first and second outputs are the outputs of the key and the threshold unit, respectively.

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