RU2517424C1 - Frequency synthesiser with switched frequency reduction channels - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: device includes two frequency-phase detectors (1 and 9), two low-pass filters (2 and 10), a voltage-controlled generator (3), a power splitter (4), a frequency divider (5), a low-frequency switch (6), a mixer (7), a reference frequency generator (8) and a control unit (12).

EFFECT: reduced level of phase noise in the output signal, frequency tuning time and level of parasitic spectral components.

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Description

The invention relates to radio engineering and can be used to form a grid of stable frequencies with a uniform pitch in receiving devices with increased noise immunity, as well as in transceiving devices with fast tuning of operating frequencies.

In modern communication equipment, precision high-speed frequency synthesizers are used as spectrum carriers and local oscillators. The requirements for synthesizers include: a range of operating frequencies, a frequency tuning step, a frequency tuning time, a phase noise level of the output signal, a level of spurious spectral components. There are many options for constructing frequency synthesizers, among them: a passive synthesis synthesizer [1], a digital computational synthesizer (or Direct Digital Synthesizer - DDS), a phase-locked loop synthesizer (IFAP) with a divider in the feedback circuit [2], and also various combinations thereof (patents CA 2442721, US 7579916, US 7250823). Passive synthesis synthesizers provide the required level of phase noise of the output signal, but cannot provide a frequency tuning step, as well as a range of operating frequencies. Digital computing synthesizers provide frequency tuning requirements as well as phase noise level of the output signal, but the output signal of such a synthesizer has a high level of spurious spectral components and the operating frequency range is limited. In frequency synthesizers with IFAPH, the required operating frequency range and frequency tuning step are achieved, but the necessary frequency tuning step in combination with the necessary phase noise level of the output signal is not performed.

To meet the conflicting requirements for the phase noise level of the output signal, the frequency tuning time, as well as the level of the side spectral components of the output signal, while maintaining the operating frequency range and frequency tuning step, combined frequency synthesizers are used. So in [3], a construction scheme of such a frequency synthesizer is described, which includes a generator with a resonator from the sphere of yttrium iron garnet. In such a scheme, the feedback circuit contains a path for bringing the frequency of the output generator to the comparison frequency based on a mixer (or a group of mixers in the general case), to which a signal with low phase noise is applied. By using this method of reducing the frequency of the output signal of the synthesizer to the comparison frequency in the feedback circuit, the multiplication of phase noise in the passband of the phase-locked loop system inherent to IFAH synthesizers with a divider in the feedback circuit is eliminated.

The closest in technical essence to the proposed device can be considered a combined frequency synthesizer with switched frequency reduction paths described in patent 1187701299, adopted as a prototype.

An enlarged functional diagram of the prototype device is presented in figure 1, in which the group of mixers is replaced by one mixer without compromising functionality.

Figure 1 introduced the following notation:

1 - frequency-phase detector (ChFD);

2 - low-pass filter (low-pass filter);

3 - voltage controlled oscillator (VCO);

4 - power splitter (PM);

5 - frequency divider (DC);

7 - mixer;

8 - reference frequency driver (FOC);

11 - high-frequency switch (VK).

The prototype device contains a series-connected frequency-phase detector (ChFD) 1, a low-pass filter (LPF) 2, a voltage-controlled oscillator (VCO) 3, and a power splitter (PM) 4, the first output of which is the output of the device; the second output of PM 4 through a frequency divider (DC) 5 is connected to the first input of the high-frequency switch (VK) 11, the third output of PM 4 is connected to the first input of the mixer 7, the second input of which is connected to the first output of the reference frequency driver (FOC) 8, and the output mixer 7 is connected to the second input of BK 11, the output of which is connected to the second input of the PSD 1, the first input of which is fed a signal from the second output of the reference frequency driver (FOC) 8, the input of which is connected to the reference generator (OG).

The prototype device operates as follows.

The exhaust signal is fed to the input of the FOC 8, in which signals with the necessary frequencies are generated (for example, using a set of multipliers and frequency dividers). FOCH from the second output 8 signal with frequency f _og supplied to the first input of the PFD 1, the second input of which through blocks VC 11 PM and 5 PM 4 receives the signal of the VCO 3. In the PM 5 frequency f _O of the VCO output signal is divided into 3 N times in order to bring its value to the frequency of the exhaust gas f _og . The error signal from the output of the PFD 1 through the low-pass filter 2 is fed to the control input of the VCO 3, the frequency of the output signal of which f _o changes until divided by N times (N in the general case can be either integer or fractional) in the RF unit 5, it will not be equal to the frequency of the exhaust signal f _og . In this case, the output voltage at the output of the VFD unit 1 ceases to change, and the frequency of the output signal of the VCO unit 3 f _ov becomes equal to the exhaust gas frequency f _og times N times.

This state of the phase-locked loop system is called synchronism [2]. The output signal of the VCO 3 with a given frequency is fed to the input PM 4, from the first output of which is supplied to an external load. Thus, the device output signal frequency is determined by the expression f _O = Nf _Og. By multiplying the frequency of the output signal of the VCO 3, the phase noise of the output signal of the device in the passband of the PLL system is the multiplied phase noise of the reference signal from the second output of the FOC 8 (summed with the noise of the detector, etc.) [2], which are determined by the phase noise of the signal reference generator. After the occurrence of the synchronism signal switching occurs at the second input of the PFD 1, to which through the mixer 7 and RM 4 is fed the output signal of the VCO 3. The second input of the mixer 7 is supplied the output signal from the first output FOCH 8, this signal frequency is chosen to be f = f _{O foch} -f _og . In the mixer 7, the output signal of the VCO 3 is multiplied with the signal of the first output of the VOC 8, due to which the output of the mixer 7 generates a signal with a frequency equal to the difference between the frequencies of the output signal of the VCO 3 unit and the VOC unit 8 f _out -f _foc (or f _foc - f _o , depending on the selected frequency generation of the device. For the sake of simplicity of description, hereinafter we will assume the output signal of the mixer with a frequency f _o -f _background ). So, the frequency of the output signal of the VCO 3 unit is brought to the frequency f _og . Due to the equality f _og = f _out -f _foc or f _og = f _out - (f _out -f _og ) excludes the frequency of the exhaust gas and, therefore, the multiplication of the phase noise of the output signal in the passband of the phase-locked loop, which in this case are determined by the sum of the phase noise of the reference signal from the second output of the low-pass filter 8 and the phase noise of the output signal of the low-pass filter 8. Due to the possibility of using the low-pass filter 2 with a wide passband, the required “small” frequency tuning time is realized.

Given the above, the disadvantage of the prototype device is the need for switching the passband of the low-pass filter unit 2 due to a change in the multiplication coefficient K, which, in the case of large values of N, is an intractable problem.

The problem to which the invention is directed, is to reduce the level of phase noise of the output signal of the frequency synthesizer, the frequency tuning time, as well as the level of spurious spectral components.

The technical result achieved is the combination in one device of the advantages of frequency synthesizers with a wideband IFAPH with a divider in the feedback circuit in terms of speed, with the advantages of a frequency synthesizer with a mixer and an analog frequency reduction path in the feedback circuit in terms of the phase noise level of the output signal. At the same time, the possibility of autonomous operation of the frequency synthesizer with IFAPCH with a divider in case of failure of the analog frequency reduction path is realized.

To solve the problem in a frequency synthesizer, containing a series-connected first frequency-phase detector (ChFD1) and the first low-pass filter (LPF1); a voltage-controlled oscillator (VCO) and a power splitter (PM) connected in series, the first output of which is the output of the device; frequency divider (DC), the input of which is connected to the second output of the PM; a mixer, the first input of which is connected to the third output of the PM; a reference frequency shaper (FOC), to the input of which a reference oscillator (OG) signal is supplied, the first FOC output is connected to the second input of the mixer, and the second FOC output is connected to the first input of BFD1, according to the invention, a low-frequency switch (NK), a control unit are additionally introduced (BU) and a second frequency-phase detector (ChFD2) and a second low-pass filter (LPF2) connected in series; wherein the output of the PM is connected to the second input of BFD1, the second output of which is connected to a single input of the control unit, the group of inputs of which is connected by bus to an external control device, and the group of outputs of the control unit via the control bus is connected to the groups of control inputs of the VF, DF, and NK, the first and second the inputs of which are connected respectively to the outputs of the low-pass filter 1 and low-pass filter 2, and the output of the NK is connected to the input of the VCO; the mixer output is connected to the second input of ChFD2, the first input of which is connected to the third output of the FOC.

A block diagram of the inventive device is shown in figure 2, where the following notation is introduced:

1 - the first frequency-phase detector (ChFD1);

2 - the first low-pass filter (LPF1);

3 - voltage controlled oscillator (VCO);

4 - power splitter (PM);

5 - frequency divider (DC);

6 - low-frequency switch (NK);

7 - mixer;

8 - reference frequency driver (FOC);

9 - second frequency-phase detector (ChFD2);

10 - the second low-pass filter (LPF2);

12 - control unit;

13 - control bus.

The inventive device comprises a series-connected first frequency-phase detector (BFD1) 1 and a first low-pass filter (LPF1) 2, the output of which is connected to the first input of the low-frequency switch (NK) 6; connected in series with a second frequency-phase detector (ChFD2) 9 and a second low-pass filter (LPF2) 10, the output of which is connected to the second input of the NK 6, the output of which through a voltage-controlled generator (VCO) 3, is connected to the input of a power splitter (PM) 4, the first output of which is the output of the device, the second output through a frequency divider (DC) 5 is connected to the second input of the PDF1 1, and the third output of PM 4 is connected to the first input of the mixer 7, the output of which is connected to the second input of the PDF2 9, and the second input is with the first output of the support shaper frequency (FOC) 8. In addition, the device contains a control unit (CU) 12, the group of outputs of which is connected via a control bus (CW) 13 with groups of control inputs NK 6, PM 5 and FOC 8, to a single input of which a signal from the reference generator (exhaust). In this case, the group of inputs of the control unit 12 is connected via a bus (standard bus SPI or USB) to an external control device (VUU), and a single input of the control unit 12 is connected to the second output of the BFD1 1, the first input of which is connected to the second output of the FOC 8, the third output of which connected to the first input of ChFD2 9.

BU 12 can be implemented on the basis of a microcontroller (for example, a microcontroller C8051Fxxx from Silicon Laboratories). The functioning algorithm of block 12 is shown in FIG.

The inventive device operates as follows.

In the initial state, the control unit 12 is in standby mode commands from the WUU (block 12.1 in figure 3). After receipt of a command to record the frequency of the output signal of the frequency synthesizer in the control unit 12 from the control unit via a standard exchange protocol (for example, Serial Peripheral Interface - SPI or Universal Serial Bus - USB), a switching signal is generated in block 12.2, which is sent to NC 6 via control unit 13 which switches the output of the low-frequency filter 1 2 with the input of the VCO 3. In this case, the switch can be an electronic key, for example, the ADG713 Analog Devices chip, in which switching is performed by a logic signal “0” or “1” on the corresponding control output. Next, in block 12.3, the division coefficient N is calculated according to the ratio:

$$\text{N}=\frac{{\text{f}}_{\text{out}}}{{\text{f}}_{\text{og1}}},\text{(one)}$$

where f _o - the frequency of the output signal of the device;

f _og1 - the frequency of the signal at the second output of the FOC 8.

The obtained value of N by means of the ШУ 13 through the block 12.4 is recorded in the block PM 5.

The first input of the BFD1 1 receives a signal from the second output of the FOC 8 (in general, the signal of the reference generator can be transmitted to the first input of the BFD1 1 without converting its frequency to FOC 8. Thus, hereinafter, for simplicity of description, we assume that the signal of the reference the generator passes through FOC 8 with frequency conversion by R times, where R, in addition to integer and fractional values, can take the value “1”), and the signal from the VCO 3 output, the frequency of which is divided by N times in the PM unit 5. Signal frequency mismatch signal in arriving at the first and second inputs CHFD1 1, the output CHFD1 1 is input FNCH1 2, where allocated its dc component, which through NC 6 is fed to the control input of the VCO 3, which is the output frequency f _O is changed to until divided into N times (N in the general case may be either integer or fractional) in block 5 PM, it will not be equal to the frequency f _og of the signal from the second output FOCH 8. in this case, the output voltage at the output ceases to vary CHFD1 1 and the output frequency f _O of the VCO 3 becomes equal to the frequency f oG1 _og1 multiplied th N times, ie, the phase-locked loop system enters the state of synchronism (block 12.5). The output signal of the VCO 3 with a given frequency is fed to the input PM 4, from the first output of which is supplied to an external load. Thus, the device output signal frequency is determined by the expression f _O = N · f _og1. Similarly with the prototype device, the phase noise of the output signal of the device is the multiplied phase noise of the signal from the second output of the FOC 8, which are determined by the noise of the reference generator.

After the onset of synchronism, a synchronism signal is generated at the second output of the BFD1 1. In many modern microcircuits (for example: ADF4158 Analog Devices, HMC704LP4E Hittite, etc.) there is a digital output “LockDetect”, showing a logic signal (“0” or “1” depending on the microcircuit) the presence of synchronism in the frequency synthesizer. After the synchronism signal arrives at the single input of the control unit 12, in block 12.6, the frequencies are calculated and the codograms of the output signals of the first f _oc2 and the third f _foc = f _output -f _{oc2 of the} outputs of the _FOC 8 (the signal at the first output of the FOC 8 can be generated with using a set of multipliers and frequency dividers, a harmonic generator, digital computational synthesizers, etc.) and writing the necessary commands through ШУ 13 in ФОЧ 8. Then, in block 12.7, a switching signal is generated, which is supplied through ШУ 13 to НК 6, whereby the signal from exit LPF2 10 is fed to the control input of the VCO 3. At the same time, the signal from the third output of the VFCH 8 is supplied to the first input of the VFD2 block 9, and the output signal of the mixer 7, in which the frequency of the output signal of the VCO 3 f _o coming to the input of the mixer 7 through the PM 4 unit, due to mixing it with the output signal of the _FOC unit 8 f _foc = f _out -f _oc2 , to the frequency of the signal from the third output of the FOC 8 f _oc2 . The mismatch signal of the frequencies supplied to both inputs of the BFD2 9 signals is fed to the input of the low-pass filter 2, where its constant component is extracted, which is fed to the control input of the VCO 3. The frequency of the output signal changes until the equality f _og2 = f _out -f _foc or f _og2 = f _out - (f _out - f _og2 ). After the equality f _og2 = f _out -f _{foc, the} voltage at the output of ChFD2 9 ceases to change, and the frequency of the output signal of the device becomes equal to f _out = f _out + f _foc .

Thus, by using two frequency-phase detectors and, therefore, by choosing a high frequency _fg it is possible to reduce the value of the coefficient N, and by choosing a lower frequency _fg1 it is possible to choose a reference signal source with lower phase noise of the output signal. Moreover, by reducing N, the task of switching low-pass filters in the control channel of the phase-locked loop system is simplified.

Thus, the implementation of the invention makes it possible to combine in one device the advantages of frequency synthesizers with IFAPH with a divider in the feedback circuit in terms of speed, with the advantages of a frequency synthesizer with a mixer and an analogue frequency reduction path in the feedback circuit in terms of the phase noise level of the output signal. In this case, it is possible to realize the autonomous operation of the frequency synthesizer with IFAPH with a slight deterioration of the spectral characteristics in the event of failure of the analog frequency reduction path, which increases the reliability and applicability of the device.

Information sources

1. Manassevich V. Frequency synthesizers. Theory and design. Translated from English by V.A. Povzner, ed. A.S. Galina. - M .: Communication, 1979

2. Frequency synthesizers with a pulse-phase self-tuning system // Levin VA, Malinovsky VN, Romanov S.K. - M .: Radio and communications, 1989.

3. Belchikov S.A. Phase noise: how to go down below -120 dB / Hz at a detuning of 10 kHz in the frequency range up to 14 GHz, or the Struggle for decibels // Components and Technologies, No. 5, 2009, p.139-146.

Claims (1)

A frequency synthesizer comprising a series-connected first frequency-phase detector (ChFD1) and a first low-pass filter (LPF1); a voltage-controlled oscillator (VCO) and a power splitter (PM) connected in series, the first output of which is the output of the device; frequency divider (DC), the input of which is connected to the second output of the PM; a mixer, the first input of which is connected to the third output of the PM; reference frequency driver (FOC), to the input of which a reference oscillator (OG) signal is supplied, the first FOC output is connected to the second input of the mixer, and the second FOC output is connected to the first ChFD1 input, characterized in that a low-frequency switch (NK) is additionally introduced into it , a control unit (BU) and a second frequency-phase detector (ChFD2) and a second low-pass filter (LPF2) connected in series; wherein the output of the PM is connected to the second input of BFD1, the second output of which is connected to a single input of the control unit, the group of inputs of which is connected by bus to an external control device, and the group of outputs of the control unit via the control bus is connected to the groups of control inputs of the VF, DF, and NK, the first and second the inputs of which are connected respectively to the outputs of the low-pass filter 1 and low-pass filter 2, and the output of the NK is connected to the input of the VCO; the mixer output is connected to the second input of ChFD2, the first input of which is connected to the third output of the FOC.

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