RU184877U1 - High Frequency Spectrum Purity Synthesizer - Google Patents

Abstract

The proposed utility model relates to radio engineering and can be used to form a grid of stable frequencies with a uniform pitch in receivers with increased noise immunity, as well as in transceivers with high purity of the output signal spectrum and fast tuning of the operating frequencies.

The technical result is an increase in the speed of the frequency synthesizer and a decrease in the spectral power density of the phase noise.

To achieve a technical result, a splitter (4) and a first key of Cl ₁ are inserted in series with one output of which is connected to the input of a second frequency divider with a fixed division coefficient (DPCD) (2.1), the output of which is through a second frequency-phase detector (ChFD) (2.2) connected to the input of the second switch Kl _2, the outputs of which, respectively through the second (2.3) and third (2.6) low-pass filters (LPF) connected to respective inputs of the third key Kl _3, whose output is connected to the input of the second oscillator by controlling voltage (VCO) (2.4), the output of which is the second output of the frequency synthesizer and through the second fractional frequency divider with a variable division coefficient (DPCD) (2.5) is connected to the other input of the second ChFD (2.2), while the outputs of the microcontroller (6) are bus connected to the control inputs of the first, second and third keys, respectively; the other output of the splitter is connected to the input of the first DPCD (1.1); the output of the first VCO (1.4) through a frequency divider (5) is connected to the corresponding input of the first key Cl ₁ . 2 ill.

Description

The proposed utility model relates to radio engineering and can be used to form a grid of stable frequencies with a uniform pitch in receivers with increased noise immunity, as well as in transceivers with high purity of the output signal spectrum and fast tuning of the operating frequencies.

The technique for reducing the MSS level in the spectrum of the output signal of a frequency synthesizer (MF) is that in order to avoid intermodulation spurious spectral components (MSS) (beat of the output frequency with the n-harmonic of the frequency of the reference oscillator), it is necessary to change the frequency of the reference signal by switching the reference oscillators ( Romanov S.K., Tikhomirov N.M., Lenshin A.V. Pulse-phase self-tuning systems in frequency synthesis and stabilization devices: monograph.M.: Radio and Communications, 2010. 328 p., Levin V.A., Malinovsky V.N., Romanov S.K. Synthesizers frequencies with a pulse-phase self-tuning system. M.: Radio and communications, 1989. 232 p.). Moreover, the necessary requirement is the non-repetition of two (or more) reference frequencies to each other. This option eliminates the increase in noise of the output signal, but has a number of disadvantages, including: increased power consumption, high cost and cumbersome.

In the description of the integrated circuit of the company HittieHMC833 for avoiding intermodulation MSS it is proposed to use the cascade connection of two fractional frequency synthesizers. With this inclusion, the output signal of the first midrange is the reference signal for the second midrange that forms the output signal. In this case, the first MF can produce a discrete set of non-multiple frequencies, by changing which, according to a certain algorithm (pre-calculated or experimentally established), integer MSSs in the spectrum of the output signal of the second MF can be avoided. This technique also has several disadvantages: an increase in the spectral power density (PSD) of phase noise (FS), and an increase in the frequency setting time.

The closest analogue in technical essence to the proposed one is a frequency synthesizer according to the patent of the Russian Federation 2458461, H03L 7/16, 7/06, adopted as a prototype.

The circuit of the prototype device is shown in FIG. 1, where the following notation is accepted:

1.1 - frequency divider with a fixed division ratio (DPCD);

1.2 - frequency-phase detector (ChFD);

1.3 - low-pass filter (low-pass filter);

1.4 - voltage-controlled generator (VCO);

1.5 - fractional frequency divider with a variable division ratio (DPKD);

3.1, 3.2 - the first and second signal generator of the reference frequency;

6 - microcontroller;

7.1, 7.2 - the first and second electronic on / off switch.

The prototype device contains a series-connected first electronic on-off switch 7.1, a second signal generator of a reference frequency 3.2, a second electronic on-off switch 7.2, a frequency divider with a fixed division coefficient (DFC) 1.1, a frequency-phase detector 1.2, a low-pass filter 1.3 and a generator controlled voltage 1.4, one output of which is the output of the device, and the other output through the DPKD 1.5 is connected to the second input of the CFD 1.2. In addition, the second output of the first electronic on-off switch 7.1 through the first signal generator of the reference frequency 3.1 is connected to the second input of the second electronic on-off switch 7.2. The output of the microcontroller 6 is connected to the bus with the corresponding inputs of the first 7.1 and second 7.2 electronic two-position switches, DFKD 1.1 and DPKD 1.5.

The prototype device operates as follows.

When the frequency synthesizer is turned on at a given frequency, the microcontroller 6 outputs signals in binary code to four inputs: the second input of DPKD 1.5, setting the fractional division coefficient of the DPKD in it, the input of the control signal, setting the division coefficient of the DPKD in it, and the input of the control signal the first electronic on-off switch 7.1, connecting the input of the controlled signal in it with its first output, the input of the control signal of the second electronic on-off switch 7.2, connecting in it od control signal to its output. The signal from the second output of the VCO 1.4 through the DPKD 1.5 and the signal from the output of the first generator 3.1, the second switch 7.2 and DFKD 1.1 are fed to the corresponding inputs of the frequency-phase detector 1.2, from the output of which the signal goes to the input of the VCO 1.4, which after a certain period of time provides in synchronism of the frequency of the VCO 1.4 with the frequency of the oscillator 3.1 in the phase locked loop, based on the generator 1.4. At the first output of the VCO 1.4, a synthesized frequency is formed equal to the frequency of the signal of the first generator of the reference frequency 3.1 times a specified number of times. In the synthesizer operating mode, from the output of the microcontroller 6, signals in binary code are sent to the second input of DPKD 1.5, setting the fractional division coefficient of DPKD in it, to the input of the control signal DFKD 1.1, setting the division coefficient of DFKD 1.1 in it, to the input of the control signal of the first switch 7.1, connecting in it the input of the controlled signal with its second output, the input of the control signal of the second switch 7.2, connecting in it the second input of the controlled signal with its output. After a certain period of time, synchronization is achieved in the phase-locked loop based on the VCO 1.4, at the first output of which a frequency is formed equal to the frequency of the signal of the second generator 3.2 times a specified number of times. In this case, the exclusion of frequency sections in which there is a high level of incidental spectral components. The digital part of the frequency synthesizer, which includes a fractional frequency divider 1.5 with a variable division ratio, a frequency divider 1.1 with a fixed division coefficient and a frequency-phase detector 1.2, can be performed on one of the microcircuits of a digital frequency synthesizer with a pulse-phase self-tuning frequency, for example manufactured by Hittite chip NMS 700/701/702 or 704. The first 7.1 and second 7.2 switches can be made on the chips IRF7317 company National e Rectifier and NMS349 company Hittite, respectively.

The disadvantage of the prototype device is that to ensure high spectral characteristics of the output signal of the midrange generators are used with a low noise level. These generators have a very high cost. Also, the use of these generators significantly increases the power consumption of the midrange and inevitably leads to an increase in the overall dimensions of the system as a whole. In addition, due to the decrease in the PSD FSH, the prototype device uses a filter with a narrow passband, which inevitably leads to an increase in the setup time of the frequency synthesizer.

The task is to increase the speed of the frequency synthesizer and reduce the spectral power density of the phase noise power.

In contrast to the technical solutions described in the publications, the proposed frequency synthesizer uses only one reference oscillator. The signal of the fixed frequency synthesizer (FSF) is used as the second reference signal.

To solve the problem in a high-speed frequency synthesizer with a high spectral purity, containing a reference oscillator, connected in series with a first frequency divider with a fixed division coefficient (DPCD), a first frequency-phase detector (ChFD), a first low-pass filter (LPF), a first generator, voltage-controlled (VCO) and the first fractional frequency divider with a variable division ratio (DPKD), the output of which is connected to the second input of the first ChFD, while the output of the first VCO is the first output of the synthesizer frequencies, as well as a microcontroller, according to a utility model, a splitter and a first key are introduced in series, one output of which is connected to the input of the second DPCD, the output of which through the second PSD is connected to the input of the second key, the outputs of which are connected through the second and third low-pass filters to the corresponding inputs the third key, the output of which is connected to the input of the second VCO, the output of which is the second output of the frequency synthesizer and through the second fractional DPKD is connected to the other input of the second CFD, while the outputs are micro the ontroller bus is connected to the control inputs of the first, second and third keys, respectively; the other output of the splitter is connected to the input of the first DPCD; the output of the first VCO through a frequency divider is connected to the corresponding input of the first key.

A block diagram of the proposed device is shown in figure 2, where indicated:

1 - fixed frequency synthesizer (FSF);

2 - tunable frequency synthesizer (PSC);

1.1, 2.1 - the first and second frequency divider with a fixed division ratio (DPCD);

1.2, 2.2 - the first and second frequency-phase detector (ChFD);

1.3, 2.3, 2.6 - the first, second and third low-pass filter (low-pass filter);

1.4, 2.4 - the first and second voltage-controlled generator (VCO);

1.5, 2.5 - the first and second fractional frequency divider with a variable division ratio (DPKD);

3 - reference generator (OG) (reference frequency signal generator);

4 - splitter (P);

5 - frequency divider (DC);

6 - microcontroller;

Cl ₁ , Cl ₂ , Cl ₃ - first, second, third keys.

The proposed device contains a series-connected reference oscillator 3 and a splitter 4, one of the outputs of which is connected to the input of a fixed frequency synthesizer 1, and the other to the corresponding input of the first key Cl ₁ , the output of which is connected to the input of the tunable frequency synthesizer 2. At the same time, the FSF 1 contains the first DPCD 1.1, the first ChFD 1.2, the first low-pass filter 1.3 and the first VCO 1.4, the output of which is the output of the FSF 1 and connected through the first DPKD 1.5 to the second input of the first ChFD 1.2 and also through the divider Oty 5 - with the corresponding input of the first key Cl ₁ . In addition, the input of the first DFKD 1.1 is the input of the FSF 1.

PSCH 2 contains series-connected second DFKD 2.1, ChFD 2.2 and Kl ₂ , the outputs of which are connected respectively through the second 2.3 and third 2.6 low-pass filters with the corresponding inputs of the third Kl ₃ , the output of which is connected through the second connected VCO 2.4 and the second DPKD 2.5 to the corresponding the entrance of the second PSF 2.2. Moreover, the output of the second VCO 2.4 is the output of PSCh 2; the input of the second DFKD 2.1 is the input of the MSC 2. Moreover, the outputs of the microcontroller 6 are connected by a bus to the control inputs of the keys Cl ₁ , Cl ₂ and Cl ₃ .

The inventive device operates as follows.

When operating in normal mode, the reference signal from the exhaust gas output 3 is fed to splitter 4 and from one output of splitter 4 is fed to the input of the first DFKD 1.1 of the fixed frequency synthesizer 1. Then, from the output of DFKD 1.1, the divided reference signal is fed to one of the inputs of the BFD 1.2 whose input through the first DPKD 1.5 receives the signal from the output of the first VCO 1.4. The frequency mismatch signal from the output of the first ChFD 1.2 through the first low-pass filter 1.3 is fed to the input of the VCO 1.4, the frequency of the output signal of which changes until divided by a predetermined number of times in the first DPKD 1.5, it will not be equal to the frequency of the exhaust signal 3. In this case , the output voltage at the output of the ChFD block 1.2 ceases to change, and the frequency of the output signal of the VCO 1.4 becomes equal to the frequency of exhaust gas 3 multiplied by a predetermined number of times, i.e. the phase-locked loop system of the FSF 1 enters a state of synchronism.

From the second output of splitter 4, the reference signal through the first key of Cl _{1 is} fed to the input of the second DFKD 2.1, from the output of which the divided reference signal is fed to one of the inputs of the PDF 2.2, to the second input of which through the block of the DPKD 2.5 the signal from the output of the VCO 2.4 comes. The frequency mismatch signal from the output of the ChFD 2.2 through the second key of Cl ₂ is fed to the input of the low-pass filter 2.3 with a wide passband to reduce the frequency setting time, from the output of which the control signal through the third key of Cl ₃ enters the input of the VCO 2.4, the frequency of the output signal of which changes to those until, divided by a predetermined number of times in the DPKD 2.5 block, it will not be equal to the frequency of the exhaust gas signal 3. In this case, the output voltage at the output of the ChFD 2.2 block ceases to change, and the frequency of the output signal of the VCO 2.4 block becomes equal to the exhaust gas frequency 3, at multiplied by a given number of times, i.e. the phase-locked loop system of the ПСЧ 2 enters a state of synchronism. After this, after a certain period of time, the microcontroller 6 switches the keys K ₂ and K ₃ to a different position, as a result of which the third low-pass filter 2.6 with a narrow passband is used in the PLL system PSCh 2 to reduce SPMSF. In the process of operation, when switching the MSS 2 to frequencies that are multiples of the frequency of the exhaust gas 3, intermodulation MSS appear in the spectrum of the output signal of the MSC 2. To avoid these MSSs, K ₁ is switched, and the output divided frequency of the MSS is used as the exhaust gas signal 3 for the MSS 2.

Thus, the technical result of the proposed utility model is an increase in the speed of the frequency synthesizer and a decrease in the spectral power density of the phase noise.

Claims (1)

A high-frequency high-purity frequency synthesizer containing a reference oscillator, a first fixed frequency division divider (DFC), a first frequency-phase detector (ChFD), a first low-pass filter (LPF), a first voltage-controlled oscillator (VCO), connected in series , and the first fractional frequency divider with a variable division coefficient (DPKD), the output of which is connected to the second input of the first PSD, while the output of the first VCO is the first output of the frequency synthesizer, as well as a microcontroller, characterized in that a splitter and a first key are introduced in series, one output of which is connected to the input of the second DPCD, the output of which through the second PSD is connected to the input of the second key, the outputs of which are connected through the second and third low-pass filters to the corresponding inputs of the third key, the output of which is connected with the input of the second VCO, the output of which is the second output of the frequency synthesizer and through the second fractional DPKD is connected to another input of the second ChFD, while the outputs of the microcontroller are connected to the control bus General inputs of the first, second and third keys, respectively; the other output of the splitter is connected to the input of the first DPCD; the output of the first VCO through a frequency divider is connected to the corresponding input of the first key.

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