RU2414742C1 - Apparatus for repacking streams for inputting data - Google Patents

Abstract

FIELD: information technology. ^ SUBSTANCE: apparatus includes a logic unit with a clock signal input and eight data inputs, a 64 bit FIFO register, whose inputs are connected to corresponding inputs of the computer system bus controller, which is connected to the system bus. The logic unit includes a multiplexer, a latch register with 448 cells, an adaptive demultiplexer, 8 data stream distributors, a control unit, wherein the output 64-bit bus of the multiplexer is connected to the corresponding input bus of the FIFO register. Outputs of the latch register are combined into 64 bit buses, which are connected to corresponding inputs of the multiplexer, and outputs of the latch register are connected to inputs of the adaptive demultiplexer, 32 outputs of the data stream distributors are connected to 32 inputs of the adaptive demultiplexer, and inputs of the distributors are connected to corresponding data inputs. A clock signal is transmitted to one input of the control unit and a signal which corresponds to the number of input channels, which varies from 1 to 8, is transmitted to the other input. ^ EFFECT: repacking data for any number of input streams from 1 to 8 without the need for strict synchronisation of output streams on clock frequencies. ^ 3 dwg

Description

The invention relates to digital signal processing systems and is intended for repackaging data streams.

When processing information on computers, it is often a task to enter data through several channels, and their number can quickly change, for example, from one to eight, which requires data repackaging.

Known and widely used are such devices for repackaging data streams, such as multiplexers and demultiplexers [1], implemented on specialized integrated circuits or on FPGAs.

Also, as analogs, one can cite the selected ISERDES circuit components that are part of the Virtex4 family of Xilinx FPGAs [2]. Their main element is shift registers. The ISERDES component provides repacking from 1 stream to 2-8 threads. These circuit components have significant drawbacks. These components fundamentally require tight synchronization of input and output streams. Their operation requires two multiple clock frequencies. For ISERDES, the output clock frequency should be 2-8 times less than the input clock (depending on the number of input streams). These components provide only parallelization of one stream entering the FPGA into several threads. However, these components do not provide a solution to the problem of entering several parallel threads.

As the closest to the claimed technical solution, we can cite a device containing SN74LV164 microcircuits from Texas Instruments [3], which allow repackaging signals from one stream to 8, a logic block with a clock input and eight data inputs, a 64-bit FIFO register having a control input and outputs connected to the corresponding inputs of the system bus controller connected to the PC system bus.

In a known device, a clock signal is supplied to the inputs, the frequency of which corresponds to the frequency of the input data. The computer system bus controller transfers data from the FIFO register to the system bus.

Then, using eight SN74LV164 microcircuits, 8 input data streams are parallelized into 64 streams of lower speed. To synchronize the operation of the SN74LV164 chips and write data to the FIFO register, a clock signal with a frequency of 1/8 of the frequency of the input clock signal generated by the counter is used.

The disadvantage of this device is the fixed repackaging structure.

The technical result of the present invention is the implementation of repackaging for any number of input streams from 1 to 8 and without the need for tight synchronization of input streams at clock frequencies.

A device is proposed for repackaging data streams, which solves the problem by intermediate conversion of several input data streams, the number of which can vary from 1 to 8, into a single 64-bit stream. Such a stream is suitable for exchanging data with the buffer of the PC system bus controller, which ensures data input into the PC.

The technical result is achieved by the fact that in the proposed device for repackaging streams for data input, having a logic unit with a clock input and eight outputs for data, a 64-bit FIFO register, the outputs of which are connected to the corresponding inputs of the PC system bus controller connected to the system bus, according to the invention, an adaptive demultiplexer, a register-latch with 448 cells, a multiplexer, 8 data flow distributors, a control unit, and an output 64-bit bus the lithiplexer is connected to the corresponding input bus of the FIFO register, the outputs of the register-latch are combined into 64-bit buses, which are connected to the corresponding inputs of the multiplexer, and the inputs of the register-latch are connected to the outputs of the adaptive demultiplexer, 32 outputs of the distributors of data streams are connected to 32 inputs of the adaptive demultiplexer, and the inputs of the valves are connected to the corresponding data inputs, a clock signal is supplied to one input of the control unit, a signal corresponding to the number travel channels, which can vary from 1 to 8; moreover, from the outputs of the control unit, a write signal is applied to the control input of the FIFO register, an address signal of 64-bit data groups is sent to the control inputs of the multiplexer, a quarter-frequency signal of the input clock signal and an address signal to write data to the latch register are sent to the control inputs of the register-latch , an addressing signal is supplied to the control input of the adaptive demultiplexer, signals of the input clock frequency and a quarter of the input clock frequency are fed to the control inputs of the data distributors.

Further description is explained using the following figures.

Figure 1 - Structural diagram of the proposed device for data entry. Figure 2 - Block diagram of the input control unit. Figure 3 - Timing diagrams of the proposed device for the case of data entry on 7 channels.

The device can be implemented as follows. The device for repackaging streams for data input contains a logic unit 1 with a clock signal input Clk_in, an input for the number of NC input channels and eight data inputs, a 64-bit FIFO 2 register, the outputs of which are connected to the corresponding inputs of the system bus 3 controller connected to the PC system bus 4. Logic block 1 contains an adaptive demultiplexer 5, a register-latch 6 with 448 cells, a multiplexer 7, 8 of distributors 8..15 data streams, a control unit 16, while the output 64-bit bus of the multiplexer 7 is connected to the corresponding the current input bus D_fifo register FIFO 2, the outputs of the register-latch 6 are combined in the bus Gr1..Gr7 of 64 bits, which are connected to the corresponding inputs of the multiplexer 7, and the inputs D_Per of the register-latch 6 are connected to the outputs of the adaptive demultiplexer 5, 8 4-bit the outputs Gr1_in..Gr8_in of the data flow distributors 8..15 are connected to the corresponding inputs of the adaptive demultiplexer, and the inputs of the combiners 8 .. 15 are connected to the corresponding data inputs Data_in1..Data_in8, a clock signal Clk_in is applied to one input of the control unit 16, and to the other input d NC is supplied a signal corresponding to the number of input channels, which can vary from 1 to 8; moreover, from the outputs of the control unit to the control input of the register FIFO 2, a write signal WE is supplied, to the control inputs of the adaptive demultiplexer 5, a signal Ad_DMP of the address of 4-bit data groups Grl_in..Gr7_in is supplied, to the control inputs of the register-latch 6 a quarter of the input clock frequency Clk / 4 and the address signal Ad_Per, the address signal Ad_MP is supplied to the control input of the multiplexer 7, the input clock frequency Clk_in and the fourth input clock frequency Clk / 4 signals are sent to the control inputs of the data flow distributors 8 .. 15.

Data_inl..Data_in8, code of the number of output channels NC (from 1 to 8), and clock signal Clk_in are fed to the device inputs.

Logic block 1 provides the conversion of the input n-bit data stream (n = 1, 2 ... 8) into a 64-bit stream for input into a PC by sequentially overwriting the data in the FIFO register 2, the system bus controller 3 and the PC system bus 4.

Distributors P 8 ... 15 streams are designed to parallelize each input stream Data_in on 4 streams Gr_in.

The adaptive demultiplexer (DMP) 5 performs the demultiplexing of 4n-bit data Gr_in on the 448-bit input bus D_Per register-latch 6, designed for intermediate data storage.

The multiplexer (MP) 7 multiplexes the data received from the output buses Grl..Gr7 of the register-latch 6 to transfer them to the 64-bit bus for writing to the FIFO 2 register.

The system bus controller 3 transfers data from the FIFO 2 register to the system bus of the computer 4.

The control unit 16 generates the signals necessary to control all other elements of the logical unit 1 and the register FIFO 2.

The inputs of the control unit 16 are supplied with a clock signal Clk_in and a code of the number of channels when outputting NC (three-digit binary number).

Counter 17 is used to divide the frequency of the input clock signal by 4.

Shaper 18 addresses sets the universal address for shaper 19 of the write signal WE, encoder 20 addresses of adaptive DMP 5, encoder 21 addresses MP 7 and encoder 22 addresses of the register-latch 6.

Shaper 19 WE is designed to generate a signal for recording permission of 64 data bits in FIFO 2.

The adaptive DMP address encoder 20 is a combinational logic circuit and generates an address for adaptive DMP 5.

The encoder 21 of the MP address is a combinational logic circuit and generates an address for MP 7.

The register-latch address encoder 22 is a combinational logic circuit and is designed to write data to the 4-bit register-latch cell 6.

Timing diagrams of the operation of the device for data input over 7 channels are presented in figure 3. The diagrams used the usual notation of logical units and zeros in the form of the corresponding two voltage levels. Here, the same signal designations are used as in the structural diagram of the proposed device for outputting data (Fig. 1).

It can be seen from the time diagrams that 7 input Data_in streams are converted into 7 four-bit Gr_in streams, and then into an output ascending sequence of 64-bit D_fifo data (which is a visual implementation of the input data). The signals Clk / 4 and WE are generated from the input clock signal Clk_in.

The described device provides repackaging operations of data from 1 ... 8 streams into 64 streams (required to enter data into the PC system bus) at any frequency of the input clock signals.

Thus, the goal is achieved to solve the complex problem of repacking, with extremely simple technical means. All digital signal conversions are carried out by means of logic circuitry. Therefore, the repackaging device can be easily implemented both on discrete logic elements and on the basis of programmable logic integrated circuits (FPGAs).

The effectiveness of the proposed technical solution is confirmed experimentally: the corresponding repacking device is implemented on the Xilinx family of XC4VFX20 FPGAs of the Virtex 4 family and tested for operation in a wide range of clock frequencies (up to 600 MHz).

Information sources

[1] Kalabekov B.A. Digital devices and microprocessor systems. - M .: Hotline - Telecom, 2003, p.123-126.

[2] Low-Voltage Logic Data Book. - Texas Instruments, 1996, p.10-47-10-57.

[3] Virtex-4 Libraries Guide for HDL Designs. - Xilinx, 2005, p. 153-160, p. 227-232.

Claims (1)

A device for repackaging streams for data input, having a logical unit with a clock input and eight data inputs, a 64-bit FIFO register, the outputs of which are connected to the corresponding inputs of the PC system bus controller connected to the system bus, characterized in that multiplexer, register-latch with 448 cells, adaptive demultiplexer, 8 data flow distributors, control unit, while the output 64-bit multiplexer bus is connected to the corresponding input bus reg Istra FIFO, the outputs of the register-latch are combined into 64-bit buses that are connected to the corresponding inputs of the multiplexer, and the inputs of the register-latch are connected to the outputs of the adaptive demultiplexer, 32 outputs of the distributors of data streams are connected to 32 inputs of the adaptive demultiplexer, and the inputs of the distributors are connected to the corresponding data inputs, a clock signal is supplied to one input of the control unit, a signal corresponding to the number of input channels, which can vary from 1 to 8, is supplied to another input; moreover, from the outputs of the control unit to the control input of the FIFO register, a write signal is applied, the address signal of the 64-bit data groups is fed to the control inputs of the multiplexer, a quarter of the input clock frequency and an address signal for writing to the fix register are sent to the control inputs of the register-latch the control input of the adaptive demultiplexer is supplied with an addressing signal, the input clock frequency and a quarter of the input clock frequency are fed to the control inputs of the data stream distributors.

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