KR970049268A

KR970049268A - Phase Aligner with Reference Clock

Info

Publication number: KR970049268A
Application number: KR1019950053960A
Authority: KR
Inventors: 김호건; 이동춘; 이종현
Original assignee: 양승택; 한국전자통신연구원; 이준; 한국전기통신공사
Priority date: 1995-12-22
Filing date: 1995-12-22
Publication date: 1997-07-29
Anticipated expiration: 2015-12-22
Also published as: KR0153913B1

Abstract

본 발명은 기준 클럭을 이용한 위상 정렬기에 관한 것으로, 출력 시스템 클럭과 출력 기준 클럭에 위상이 정렬하여 출력되기 위해서 동일한 위상의 읽기 클럭을 제공하는 읽기 클럭 발생수단; 시스템 클럭과 기준 클럭을 이용하여 데이타 버퍼 인에이블 클럭을 생성하는 쓰기 클럭 발생부와 상기 쓰기 클럭발생부로부터의 입력 시스템 클럭과 입력 기준 클럭에 의해 입력 데이타를 래치하는 데이타 버퍼부로 구성되어 다수의 입력 버스 제어수단을 구비하되, 상기 다수의 입력버스 제어수단은, 각각의 데이타 버퍼부에 서로 상이한 위치에 래치되어 있는 입력 데이타를 출력 시스템 클럭과 출력 기준 클럭에 위상이 정렬하여 출력되기 위해서 동일한 위상의 읽기 클럭을 제공하는 상기 읽기 클럭 발생수단으로부터 제공 받아 출력하는 것을 특징으로 한다.The present invention relates to a phase aligner using a reference clock, comprising: read clock generation means for providing a read clock having the same phase so that the phases are output to the output system clock and the output reference clock; A write clock generator for generating a data buffer enable clock using a system clock and a reference clock, and a data buffer section for latching input data by the input system clock and the input reference clock from the write clock generator are provided. Bus control means, wherein the plurality of input bus control means have the same phase in order to output the input data latched at different positions in the respective data buffer sections to the output system clock and the output reference clock. And receiving from the read clock generating means for providing a read clock and outputting the read clock.

Description

Phase Aligner with Reference Clock

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 버스의 구성도.1 is a block diagram of a bus.

제2도는 본 발명의 응용예.2 is an application of the present invention.

제3도는 본 발명의 구성도.3 is a block diagram of the present invention.

Claims

Read clock generation means (20) for providing read clocks of the same phase so that the phases are output in alignment with the output system clock and the output reference clock; A write clock generator 112 for generating a data buffer enable clock using a system clock and a reference clock, and a data buffer for latching input data by an input system clock and an input reference clock from the write clock generator 112. And a plurality of input bus control means 11, each of which is latched at a different position in each of the data buffers 111, respectively. The phase aligner using the reference clock, characterized in that the output is received from the read clock generating means (20) for providing a read clock of the same phase in order to output the output system clock and the output reference clock.

The data buffer unit 111 of claim 1, wherein the data buffer unit 111 is configured in a scan form using a buffer enable signal generated by the write clock generator 112 and a clock corresponding thereto, and according to N division, the data buffer unit 111 is divided into one bit of data. N D flip-flops 621 to 62N according to N; A multiplexer which receives the signals latched by the scan enable buffer enable signals from the N D flip-flops 621 to 62N and the read clock and system clock from the read clock generator 20 and multiplexes them to output them; 61. A phase aligner using a reference clock, comprising: 61).

2. The write clock generator (112) according to claim 1, further comprising: an N division counter (41) for generating N count signals in accordance with the number of stages of the data buffer unit (111); A demultiplexer (DMUX) 42 for demultiplexing the clocks generated by the N division of the N division counter 41 to generate a clock enable signal of each of the data buffer units 111; A retiming unit (43) for receiving the clock enable signal from the demultiplexer (42) and removing the error of the output signal waveform to output a buffer enable signal; When the input reference clock and the input clock are always input in the same phase, the input reference clock is set so that the initial position of the N division counter 41 (the point at which the counter becomes zero) occurs at the position where the input reference clock is located. And a write phase synchronizer (44) for inputting the counter reset signal and outputting the counter to the N division counter (41).

※ Note: The disclosure is based on the initial application.