RU2311731C1 - Composite fast-response analog-to-digital converter - Google Patents

Abstract

FIELD: digital engineering, applicable in devices for conversion of analog voltage to a digital code.

SUBSTANCE: the device has an m-digit parallel analog-to-digital converter of a coarse scale, n-digit parallel analog-to-digital converter difference amplifier three access-storage circuits, three memory registers, digital-to-analog converter, unit for determining the sign and inversion of negative voltages, synchronizing unit.

EFFECT: simplified construction and enhanced accuracy of analog-to-digital conversion.

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Description

FIELD OF THE INVENTION

The invention relates to the field of digital technology, in particular to composite high-speed analog-to-digital converters, and can be used in devices for converting analog voltage to digital code.

State of the art

A device for a high-speed analog-to-digital converter (ADC) is known, which contains three amplitude analyzers, two groups of differential switches on transistors and reference current sources according to the number of coarse quanta, conventionally assumed to be four, although this number can be any other, and two summing resistors. The reference voltages U ₁ , U ₁ + ΔU, U ₂ , U ₂ + ΔU are applied to the bases of the right ones according to the transistor circuit. An analog input signal is applied to the bases of the left ones according to the transistor circuit and the first inputs of all three amplitude analyzers, the second inputs of the second and third amplitude analyzers are connected to the corresponding summing resistors. The outputs of the amplitude analyzers form the output of the device. (USSR Author's Certificate No. 750722 of April 24, 78).

The disadvantage of this device is that on its basis it is almost impossible to implement an accurate (multi-bit) and at the same time high-speed ADC.

Known conveyor (pipeline) ADCs containing several series-connected cascades, and the last cascade is loaded on the exact ADC. Each stage contains an ADC, the code output of which is fed to a correction logic circuitry, which is a complete adder, and to a digital-to-analog converter (DAC) of increased accuracy with a bit capacity equal to the ADC bit capacity in general, converting this code into an analog signal, which is subtracted from the input analog signal , and the remainder goes to the amplifier with a fixed gain, the output of which is connected to the input of the next stage (Averbukh V. Principles of constructing fast ADCs, Journal of Components and Technologies, 2000, No. 1, Online version I am www.compitech.ru/html.cgi/arhiv/00_01/stat_34.htm).

A similar structure is used by Burr-Brown in all high-speed ADC series: 12-bit ADS80X, 10-bit ADS82X and ADS90X, 8-bit ADS83X and ADS93X (1999 CD-ROM Catalog, Burr-Brown Corporation).

The disadvantage of this type of ADC is the complexity due to the increased requirements for the DACs and ADCs used in the device circuit, since the bipolar signal is processed in the device cascades.

The closest in technical essence and the achieved positive effect and adopted by the authors for the prototype is a composite high-speed ADC containing an m-bit parallel ADC of a rough scale, two DC voltage sources, an arithmetic-logic unit, two exact scale digitization units; each of the blocks contains a difference amplifier, a roll-off comparator, an n-bit parallel ADC and a group of k identical current switches (where k is determined by the ratio k = 2 ^ml -1), each of which consists of a differential cascade on transistors and a current generator (Patent RF №2110887 dated 05/29/96).

The disadvantage of this ADC is the design complexity, as well as the low accuracy of analog-to-digital conversion of fast processes, accompanied by an underestimation of speed relative to the level that is potentially possible for parallel structures.

Underestimated speed and low accuracy of analog-to-digital conversion of fast processes are caused by a possible change in the input signal voltage level during fast processes, as well as by the dynamic mode of operation of the digitizing blocks of an accurate scale in the absence of any synchronizing devices and devices for selecting and storing the input signal voltage level, which inevitably leads to a continuous change of codes at the output of the off-scale comparator, which means a forced increase in time Meni code generation output arithmetic-logic unit and a general conversion errors.

Disclosure of invention

The technical result that can be achieved using the present invention is to simplify the circuit of the device and increase the accuracy of the analog-to-digital conversion of fast processes while reducing the speed to the level potentially possible for parallel structures.

The technical result is achieved by the fact that a composite high-speed analog-to-digital converter containing an m-bit parallel analog-to-digital converter of a rough scale, an n-bit parallel analog-to-digital converter, a difference amplifier, three sampling-storage schemes, three memory registers, and digital-to-analog are introduced a converter, a unit for determining the sign and inverting negative voltages, a synchronization unit, a control input, wherein the information input of the converter is connected to the first input of the first th sampling-storage scheme; the control input of the converter is connected to the input of the synchronization unit and to the second input of the first sampling-storage circuit, the output of which is connected to the input of the sign and negative invert block, the second output of which is connected to the input of the first memory register, and the first output is connected in parallel to the inputs of the second and the third sampling-storage circuits, the control inputs of which are connected to the first output of the synchronization unit; the output of the second sampling-storage circuit is connected to the non-inverting input of the difference amplifier, and the output of the third sampling-storage circuit is connected via a parallel analog-to-digital converter of the rough scale, the second memory register and digital-to-analog converter is connected to the inverting input of the difference amplifier, the output of which is through the parallel analog-to-digital converter connected to the third memory register; the memory register write control inputs are, respectively, the second, third and fourth outputs of the synchronization block, the fifth output of which is connected to the memory register reset control inputs; the outputs of the first, second and third registers of memory are respectively the outputs of the sign, high and low bits of the converter.

The unit for determining the sign and inverting negative voltages contains two analog switches, an inverting DC amplifier, a comparator, an inverter; the input of the unit for determining the sign and inverting negative voltages is connected to the inputs of the second analog switch, the inverting DC amplifier and the non-inverting input of the comparator, the inverting input of the comparator is connected to the zero bus, the output of the comparator is connected to the input of the inverter, the control input of the second analog key and the second output of the sign determination unit and inverting negative voltages; the output of the inverting DC amplifier is connected to the input of the first analog switch, the output of which, together with the output of the second analog switch, form the first output of the sign and negative voltage inverting unit.

The synchronization unit contains two differentiating circuits, four delay elements. The input of the synchronization unit is connected to the inputs of the first delay element and the second differentiating circuit; the output of the latter through the fourth delay element is connected to the fifth output of the synchronization unit; the output of the first delay element is connected to the first output of the synchronization unit and through the first differentiating circuit, the second delay element and the third delay element connected in series to the fourth output of the synchronization unit; the output of the first differentiating circuit serves as the second output of the synchronization unit, and the output of the second delay element serves as the third output of the synchronization unit.

Brief Description of the Drawings

Figure 1 shows the structural diagram of a composite high-speed analog-to-digital Converter.

Figure 2 shows the structural diagram of the unit for determining the sign and inverting negative voltages.

Figure 3 shows the structural diagram of the synchronization unit.

Figure 4 shows the timing diagrams explaining the operation of the device.

The implementation of the invention

A composite high-speed analog-to-digital converter consists of the first sampling-storage circuit (TSW) 1, the first input of which is connected to the information (analog) input of the converter; the control input of the converter is connected to the input of the synchronization unit (BS) 2 and to the second input of the first TSW 1, the output of which is connected to the input of the sign and negative inversion unit (BOS and ION) 3, the second output of the BOS and ION 3 is connected to the input of the first register memory (RP) 4, and the first output is connected in parallel to the inputs of the second and third TSWs 5 and 6, the control inputs of which are connected to the first output of BS 2; the output of the second TSW 5 is connected to the non-inverting input of the difference amplifier (UR) 7 with a gain of K = 2 ⁿ , and the output of the third TSW 6 through a parallel m-bit analog-to-digital converter (ADC) of rough scale 8, the second RP 9 and m-bit a digital-to-analog converter (DAC) 10 is connected to the inverting input of UR 7, the output of which is connected to the third RP 12 through a parallel n-bit ADC 11; inputs control recording RP 4, 9 and 12, respectively, on the n-, one and m-bits, are the second, third and fourth outputs of BS 2, the fifth output of which is connected to the reset control inputs RP 4, 9 and 12; the outputs of the first, second and third RP 4, 9 and 12 are respectively the outputs of the sign, high and low bits of the Converter.

The block diagram of the unit for determining the sign and inverting negative voltages 3 is shown in figure 2.

The input of the BOS and ION 3 is connected to the inputs of the second analog key (AK) 13, inverting DC amplifier (IUPT) 14 and the non-inverting input of the comparator (Com) 15, the inverting input of the comparator is connected to the zero bus, the output of the comparator is connected to the input of the inverter (Inv) 16, the control input of the second analog key AK 13 and the second output of the BOS and ION 3; the output of IUPT 14 is connected to the input of the first analog key AK 17, the output of which together with the output of the second AK 13 form the first output of BOS AND ION 3.

The block diagram of the synchronization unit 2 is shown in Fig.3.

Input BS 2 is connected to the inputs of the first delay element (EZ) 18 and the second differentiating circuit (DC) 19; the output of the latter through the fourth EZ 20 is connected to the fifth output of BS 2; the output of the first EZ 18 is connected to the first output of the synchronization unit and through the first connected DC 21, the second EZ 22 and the third EZ 23 connected in series to the fourth output of the BS 2; the output of the first DC 21 serves as the second output of BS 2, and the output of the second EZ 22 serves as the third output of BS 2.

The operation of the device is illustrated by the timing diagrams shown in figure 4.

The unit for determining the sign and inverting negative voltages 3 is designed to determine the sign (polarity) of the voltage level of the input signal and relay the signal further with a single transmission coefficient, and in the case of negative polarity, expose the translated inversion signal.

The unit for determining the sign and inverting negative voltages 3 works as follows.

Room 15, depending on the polarity of the input signal, forms a positive or negative threshold, which plays the role of a sign discharge (a logical unit or zero entering the second output of the BOS and ION 3 and subsequently recorded in the first RP 4), as well as the control action received at AK 17 through Inv 16 and AK 13 directly, that is, the state of AK 17 and AK 13 are reciprocal.

In the case of the input of the BOS and ION 3 signal of positive polarity:

- Com 15 forms a positive potential; the second output of BOS and ION 3 receives a logical unit; AK 13 is transferred to the open state, AK 17 is closed;

- the input signal is fed to the first output of the BOS and ION 3.

In the case of the input of the BOS and ION 3 signal of negative polarity:

- Com 15 forms a negative potential;

- the second output of BOS and ION 3 receives a logical zero;

- AK 13 is put into a closed state, AK 17 is open;

- the input signal inverted IUPT 14, is fed to the first output of the BOS and ION 3.

Thus, BOS and ION 3 actually forms the sign and the module of the broadcast signal.

The synchronization unit 2 synchronizes the operation of the device blocks, translating them at intervals of operation into the static mode by the input signal, thereby maximizing the noise immunity, accuracy and reliability of the analog-to-digital conversion as a whole with the most reduced time delays created during the operation of the device blocks. In addition, BS 2 allows you to enter the cyclic process into the work of the device blocks, which generally contributes to the achievement of one of the goals of the application - bringing the device performance to a level potentially possible for parallel structures.

The synchronization unit 2 operates as follows.

The signal (pulse) at the control input of duration t ₁ ÷ t ₂ , figure 4, a:

- by differentiation carried out by DC 19, it is converted into a short pulse - moment t ₁ (Fig. 4, b) and delayed by EZ 20 until t ₂ (Fig. 4, c), EZ 20 generates a reset signal of memory registers 4, 9, 12, arriving at the fifth output of BS 2;

- delayed EZ 18 to moments t ₄ ÷ t ₅ (Fig. 4, d), EZ 18 generates a control signal for TSW 5, 6, which arrives at the first output of BS 2.

The output signal of the EZ 18 by means of the differentiation carried out by the DC 21 is converted into a short pulse - moment t ₄ (Fig. 4, d), the DC 21 generates a recording control signal RP 4 received at the second output BS2.

The output signal of the DC 21 is delayed by the EZ 22 until t ₆ (Fig. 4, e), the EZ 22 generates a recording control signal RP 9, which is received at the third output of the BS 2.

The output signal of the EZ 22 is delayed by the EZ 23 until time t ₇ (Fig. 4, g), the EZ 23 generates a recording control signal RP 12, which is received at the fourth output of BS 2.

Composite high-speed analog-to-digital Converter operates as follows.

The pulse received at the control input of the device at time t ₁ (Fig. 4, a) allows the TSW 1 to select and store the voltage level of the input signal. Simultaneously:

- BS 2 proceeds to the formation of a reset pulse and at time t ₃ (Fig. 4, c) carries out a reset of RP 4, 9, 12 by a pulse coming from the fifth output of BS 2;

- BOS and ION 3 begins to analyze the level remembered by TSW 1.

By time tz (figure 4, a), TSW 1 completes the memorization process. In the General case, the interval t ₁ ÷ t ₂ (figure 4, a) is calculated in units of ns. (In the AD9059 ADC, the aperture time is 2.7 ns. (Http://www.gaw.ru/pdf7AD/adc/ ad9059.pdf), the sampling time of the built-in sampling-storage circuit is 1 ns. (Www.compitech.ru/ html.cgi / arhiv / 00_01 / stat_34. htm)).

By time t ₄ (Fig. 4, d), the voltage at the first output of the BOS and ION 3 is stabilized, and by the command of BS 2 coming from the first output of BS 2 to the control inputs of TSW 5 and 6, the process of memorizing the voltage level in TSW 5 and 6. In the general case, the interval t ₂ ÷ t ₄ (Fig. 4, d) is calculated in fractions of ns. It is determined primarily by the delay created by IUPT 14 (more specifically, by the time of an additional increase in the transient response of IUPT 14 from time t ₂ to time t ₄ ), (for example, the AD8009 superfast amplifier is characterized by a slew rate of 5500 V / μs, THS3001 - 6500 V / μs. (G. Volovich. Broadband integrated amplifiers. http://www.PLATAN.ru/ shem / pdf / str27-1sx.pdf)), since the speed of modern comparators is comparable with the speed of the TSW and at time t ₂ AK 17 and 13 are already in the set state.

At time t ₄ (Fig.4.d) BS 2 by means of a pulse from the second output of BS 2 to the input of the recording control RP 4, writes in RP 4 information about the polarity of the analog input signal. This information in the form of a logical zero or logical unit comes from the second output of the BOS and ION 3 to the input of RP 4.

By time t ₅ (figure 4, g) TSW 5 and 6 complete the process of memorization. In the General case, the interval t ₄ ÷ t ₅ (figure 4, d) can be one and a half to two times less than the interval t ₁ ÷ t ₂ , since the input of the TSW 5 and 6 receives signals of only one polarity, and the polarity of the input signals of the TSW 1 can alternate, which in the worst case will require a complete recharge of the capacitive element of the TSW 1, in contrast to the recharge of the capacitive elements of the TSW 5 and 6.

Upon completion of the establishment of the voltage at the output of the TSW 6, the ADC will actually have a static mode of operation according to the input signal, as a result of which the code at the output of the parallel ADC 8 of the coarse scale is stabilized and there will be no jitter of the low-order code, which will avoid random analysis errors.

The interval t ₅ ÷ t ₆ (figure 4, e), corresponds to the analysis time of the input signal parallel to the ADC 8 of the rough scale and is standardized.

At time t ₆ (Fig. 4, f) BS 2, by means of a pulse from the third output of BS 2 to the recording control input of RP 9, writes the output code of the parallel ADC 8 of the rough scale to RP 9. Since RP 9 is typical, the delay in reproducing the code at the outputs of RP 9 is standardized.

The code generated at the output of the RP 9 is converted by the DAC 10 to the voltage supplied to the inverting input of the UR 7. Since the bit depth of the parallel ADC 8 is a rough scale - m, there is a partition of the range of variation of the input voltage coming from the TSW 6 into 2 ^m identical zones voltage, each of which is equal, for example, to the value of E. The quantization error will not exceed the value of the value of E. In turn, the voltage at the output of UR 7 will take the value:

where n is the resolution of the parallel ADC 11.

Due to the operation of multiplication, the requirements for sensitivity to ADCs are 8 of a rough scale and 11 are the same.

Since it is assumed that the parallel ADC 8 of the coarse scale works with underweight, the voltage at the output of the DAC 10 will always be less than the voltage recorded in the TSW 6 (5), and the voltage at the output of the UR 7 will be of positive polarity. The latter allows the use of a unipolar ADC as a parallel ADC 11. Since the voltage signals supplied to the inputs of UR 7 are fixed, there will be a virtually static mode of the ADC for the input signal, as a result of which the code at the output of the parallel ADC 11 is stabilized and there will be no jitter of the low-order code, which will avoid random analysis errors , and also bring the interval t ₆ ÷ t ₇ (figure 4, g) to the minimum value typical for parallel ADCs.

At time t ₇ (figure 4, g) BS 2 by means of a pulse from the fourth output of BS 2 to the recording control input of the RP 12, writes to the RP 12 the output code of the parallel ADC 11.

In case of incorrect operation of the parallel ADC 8 coarse scale or DAC10:

a) the voltage at the output of the DAC 10 exceeds the voltage at the output of the TSW 5

- the voltage at the output of UR 7 will be of negative polarity, which will lead to the establishment of a parallel ADC 11, due to its unipolarity, codes with zero weight (00 ...);

b) the voltage at the output of the TSW 5 exceeds the voltage at the output of the DAC 10 by more than E

- the voltage at the output of UR 7 will exceed the value of E, which will lead to the establishment of 11 codes with a maximum weight (11 ... 1) at the output of the parallel ADC.

Both in that and in another case there will be a correction of the result of the analog-to-digital conversion. This statement is based on the following considerations:

1) as a rule, ADCs suffer from significant non-linearity of the transfer characteristic;

2) with a good ADC, an error in the conversion of the least significant bit occurs in the case of input and reference signals close in level, and due to the high steepness of the amplitude characteristics of the ADC comparators, the error value is a fraction of a percent of the quantization step, in particular, the ADC 8 of the rough scale, thereby that it does not exceed the magnitude of the quantization step of the ADC 11;

3) in the case of a conversion performed by the ADC 8 of a rough scale with an advantage, the addition of a minimum code from the ADC 11 will bring the conversion error of no more low-order bit of the ADC 11;

4) in the case of a conversion performed by the ADC 8 of a rough scale with an underweight, the addition of the maximum code from the ADC 11 will bring the conversion error of no more low-order bit of the ADC 11.

Thus, in the proposed device, unlike the prototype, there is no need to use an arithmetic-logical unit, which introduces significant time delays in the conversion process.

When the proposed device is in cyclic mode, due to the frequency of operation of the device blocks, it is possible to reduce the total time allocated to the conversion of the input signal, since the ratio of time intervals is fulfilled (Fig. 4, and):

that is, there is a shift interval t _shear .

In the prototype, this is not possible.

Due to the fact that in the proposed device, unlike the prototype, it was possible to avoid methodological conversion errors that affect the final conversion time of the analog signal, despite the introduction of guaranteed time protective intervals (delays), it can be unequivocally stated that the proposed device is rated the best indicators in comparison with the prototype according to the criterion of speed relative to the potential for parallel structures.

Thanks to the introduction of the TSW device 1, 5, 6 and tight synchronization of the device operation modes, it was possible to avoid changing the voltage level of the input signal during the conversion of fast processes, which means that it was possible to increase the accuracy of the analog-digital conversion of fast processes.

Due to the introduction of the BOZ AND ION 3 device, the input signals of the parallel ADC 8 of the rough scale always have a positive polarity with the input voltage range equal to half the dynamic range of the input signal. This, in turn, is practically equivalent to increasing the bit depth of the parallel ADC 8 of the coarse scale by one bit, which in the case of using an 8-bit ADC is equivalent to introducing 127 comparators. In other words, to ensure the same requirements for conversion accuracy in the prototype and the proposed device, instead of the m-bit parallel ADC of the rough scale used in the prototype, the proposed device requires a (m-1) -bit parallel ADC, which will make this ADC easier and his circuit will have 2 times less comparators.

All of the above will be true with respect to the parallel ADC 11. In this case, it should be noted that the prototype uses two blocks of digitization of the exact scale, containing a group of k = 2 ^ml -1 current switches, a difference amplifier, a roll-off comparator, and an n-bit parallel ADC. Therefore, it can be argued that to ensure the same requirements for the accuracy of the conversion in the prototype and the proposed device, the function of two parallel ADCs is performed by one, that is, there is a simplification of the circuit. We should not forget about the 2-k current switches used in the prototype and a significant number of which, even without taking into account the very high requirements for stability of parameters, determines the high degree of complexity of the prototype.

Claims (1)

Composite high-speed analog-to-digital converter containing an m-bit parallel analog-to-digital rough-scale converter, n-bit parallel analog-to-digital converter, difference amplifier, characterized in that three sampling-storage circuits, three memory registers, and a digital-to-analog converter are introduced into it , a unit for determining the sign and inverting negative voltages, a synchronization unit, a control input, while the information input of the converter is connected to the first input of the first sampling circuit -storage; the control input of the converter is connected to the input of the synchronization block and to the second input of the first sampling-storage circuit, the output of which is connected to the input of the sign and negative invert block, the second output of which is connected to the input of the first memory register, and the first output is connected in parallel to the inputs of the second and the third sampling-storage circuit, the control inputs of which are connected to the first output of the synchronization unit; the output of the second sampling-storage circuit is connected to the non-inverting input of the difference amplifier, and the output of the third sampling-storage circuit is connected via a parallel analog-to-digital converter of the rough scale, the second memory register and digital-to-analog converter is connected to the inverting input of the difference amplifier, the output of which is through the parallel analog-to-digital converter connected to the third memory register; the memory register write control inputs are, respectively, the second, third and fourth outputs of the synchronization block, the fifth output of which is connected to the memory register reset control inputs; the outputs of the first, second and third registers of memory are respectively the outputs of the sign, high and low bits of the converter, and the unit for determining the sign and inverting negative voltages contains two analog keys, an inverting DC amplifier, a comparator, an inverter, while the input of the unit for determining the sign and inverting negative voltage is connected to the inputs of the second analog switch, inverting DC amplifier and non-inverting input of the comparator, inverting the input of compara ora bus connected to zero, the comparator output is connected to the input of the inverter, the control input of the second analog switch and the second output unit, and determining the sign inverting negative voltages; the output of the inverting DC amplifier is connected to the input of the first analog switch, the output of which, together with the output of the second analog switch, form the first output of the negative sign sign and invert unit; the synchronization unit contains two differentiating circuits, four delay elements, while the input of the synchronization unit is connected to the inputs of the first delay element and the second differentiating circuit, the output of the latter through the fourth delay element is connected to the fifth output of the synchronization unit; the output of the first delay element is connected to the first output of the synchronization unit and through the first differentiating circuit, the second delay element and the third delay element connected in series to the fourth output of the synchronization unit; the output of the first differentiating circuit serves as the second output of the synchronization unit, and the output of the second delay element serves as the third output of the synchronization unit.

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