JP4999955B2 - Analog-to-digital converter operation test method, analog-to-digital converter, and analog-to-digital converter operation test apparatus - Google Patents

Description

  The present invention relates to an operation test method for an analog-to-digital converter, an analog-to-digital converter, and an operation test apparatus for the analog-to-digital converter, and more particularly to an operation test of a successive approximation type analog-to-digital converter using a redundancy algorithm.

  As an analog-digital converter (ADC) mounted on a microcomputer or system LSI, a successive approximation type is often used from the viewpoint of miniaturization and high accuracy.

  FIG. 1 is a block diagram illustrating a configuration example of a conventional successive approximation ADC. FIG. 2 is a diagram for explaining the conversion operation in the successive approximation ADC.

  As shown in FIG. 1, the conventional successive approximation ADC includes a comparator 12, a successive approximation control circuit 13, and a DA converter (digital-analog converter) 14. For example, the input analog signal SA is temporarily held by the sample hold circuit 11 and input to the comparator 12 as the input signal Vin.

  As shown in FIG. 2, it is assumed that the successive approximation ADC has a resolution of n bits (here, 5 bits) and the full-scale voltage is VFS. In the first step, the successive approximation control circuit 13 outputs a digital signal in which the bit value of the first bit (b1) is “1” and the bit values after the second bit (b2 to bn) are “0”. The DA converter 14 generates and outputs a reference analog signal Vr having a voltage corresponding to the digital signal. The voltage of the reference analog signal Vr in the first step is VFS / 2. The comparator 12 compares the voltage of the input signal Vin with the voltage of the reference analog signal Vr, and outputs a comparison result. The successive approximation control circuit 13 determines the bit value of the first bit (b1) based on the comparison result. For example, if Vin is larger than Vr, b1 is determined to be “1”, and if Vin is smaller than Vr, b1 is determined to be “0”.

  In the second step, the successive approximation control circuit 13 determines that b1 is the value determined in the first step, the bit value of the second bit (b2) is “1”, and the bit values of the third and subsequent bits (b3 to bn). Outputs a digital signal having "0", and the DA converter 14 generates and outputs a reference analog signal Vr corresponding to the digital signal. The comparator 12 compares the input signal Vin with the reference analog signal Vr and outputs a comparison result. The successive approximation control circuit 13 determines the bit value of the second bit (b2) based on the comparison result. Hereinafter, when the bit values of the third and subsequent bits are sequentially determined so that Vr approaches Vin, and when the bit value of the nth bit (here, the fifth bit) is determined, Vr is closest to Vin. Therefore, the digital signal is output as an AD conversion value.

  The algorithm for changing Vr so as to approach Vin while reducing the width for changing the reference analog signal Vr described above to ½ of the width changed in the previous step is called a binary conversion algorithm. In the binary conversion algorithm, an n-bit AD conversion value is determined in n steps.

  In recent years, higher speed is also required for successive approximation ADCs. In the successive approximation ADC of FIG. 1, if the comparison by the comparator 12 is not performed after the reference analog signal Vr output from the DA converter 14 is sufficiently set, an error may occur in the determination. Once the determination is wrong, the correction is impossible and a large conversion error occurs. Therefore, in order to maintain accuracy, it is necessary to lengthen the time of each step so that the reference analog signal Vr output from the DA converter 14 is sufficiently set, and it is difficult to increase the speed.

  In order to solve such a problem, a redundant conversion algorithm for determining an n-bit AD conversion value in M steps has been proposed. The redundant conversion algorithm is also called a non-binary conversion algorithm.

  FIG. 3 is a diagram for explaining a conversion operation in a successive approximation ADC using a redundant (non-binary) conversion algorithm. This example has a resolution of n bits (here, 5 bits) and performs the conversion process in M steps (here, 6 times). Assume that the full-scale voltage is VFS. In the first step, the successive approximation control circuit 13 outputs a digital signal in which the bit value of the first bit (b1) is “1” and the bit values after the second bit (b2 to bn) are “0”. The DA converter 14 generates and outputs a reference analog signal Vr having a voltage corresponding to the digital signal. In the case of 5 bits, the digital signal value (initial value) at the first step is “16”, and the voltage of the reference analog signal Vr is VFS / 2. The comparator 12 compares the voltage of the input signal Vin with the voltage of the reference analog signal Vr, and outputs a comparison result. The successive approximation control circuit 13 stores the comparison result of the first step.

  In the second step, the successive approximation control circuit 13 outputs a digital signal obtained by adding or subtracting “7” to the initial value (“16”) according to the determination result in the first step, and the DA converter 14 outputs this digital signal. A reference analog signal Vr corresponding to the digital signal is generated and output. Therefore, the digital signal value in the second step is “9” or “23”. The comparator 12 compares the input signal Vin with the reference analog signal Vr and outputs a comparison result. The successive approximation control circuit 13 stores the comparison result of the second step.

  Thereafter, after the third step, the above processing is repeated while changing the value to be added / subtracted to “5”, “3”, “2”, “1”. When the sixth step is completed, “7”, “5”, “3”, “2”, “1”, “0.5” are compared with the initial value “16”. The AD conversion value is obtained by adding / subtracting according to the above and finally subtracting “0.5”. For example, as shown in FIG. 3, when the signal level of the input signal Vin is “21.5”, the comparison result is positive, negative, positive, positive, negative, negative from the first step to the sixth step. 16 + 7−5 + 3 + 2-1−0.5−0.5 = 21.

  As shown in FIG. 3, when the initial value is “16” and the weights “7”, “5”, “3”, “2”, “1”, “0.5” are used, the signal level is −3. To +34, but the signal level range is “0” to “31”, and the other ranges are determined to be erroneous conversions.

  FIG. 4 is a diagram showing a schematic configuration of a successive approximation ADC using a redundant conversion algorithm. As shown in FIG. 4, the successive approximation ADC using the redundant conversion algorithm has a configuration similar to that of the conventional successive approximation ADC shown in FIG. 1, but the configuration of the successive approximation control circuit 13 is different. Although not shown in FIG. 1, the timing generation circuit 31 is shown in FIG. The timing generation circuit 31 generates a timing signal for controlling the operation of each unit in the ADC, and also generates a sampling signal for the sample hold circuit 11 and the like. In FIG. 4, the timing generation circuit 31 is shown to output only the sampling signal and the timing signal supplied to the successive approximation control circuit 13. However, for example, the comparator 12 also operates in accordance with the timing signal (clock). Are generally used. Further, when the DAC 14 is a charge sharing type DAC, a timing signal for switching the connection of the capacitors is supplied from the timing generation circuit 31.

  The successive approximation control circuit 13 includes a ROM 21, an adder 22, a subtracter 23, a multiplexer (MUX) 24, and a register (Reg) 25. The ROM 21 stores an initial value corresponding to Vr at the first step, a weight value to be added / subtracted to generate Vr at the second step and after, and a corresponding value according to a signal indicating the step from the timing generation circuit 31. Is output. The adder 22 adds the value output from the ROM 21 to the digital value of the previous step held in the Reg 25 and outputs the result. The subtracter 23 subtracts the value output from the ROM 21 from the digital value of the previous step held in the Reg 25 and outputs the result. The MUX 24 selects one of the output of the adder 22 and the output of the subtracter 23 according to the comparison result of the comparator 12 and outputs the selected output to the DAC 14 and the Reg 25. The DAC 14 generates Vr according to the digital signal value output from the MUX 24. Reg 25 holds the digital signal value output from the MUX 24. The output of the MUX 24 at the time when the final step is completed becomes the AD conversion value Dout.

  At the start of the conversion operation, the value of Reg25 is reset to zero, and in the first step, the adder 22 outputs an initial value, and the MUX 24 selects the output of the adder 22. In response to this, the DAC 14 generates Vr, and the Reg 25 stores the initial value. During the comparison operation of the first step, the ROM 21 outputs the weight value of the second step, and the MUX 24 selects and outputs one of the output of the adder 22 and the output of the subtractor 23 according to the comparison result of the first step. To do. Thereafter, the same operation is repeated M times.

  FIG. 5 is a diagram for explaining a change in the output Vr of the DAC 14 when changing from the second step to the third step in the successive approximation ADC. When the comparison operation of the second step is performed, the DAC 14 outputs Vr of the second step, and Vr needs to be stable in order to perform a correct comparison. Immediately after the comparison operation of the second step is completed, the MUX 24 selects and outputs one of the output of the adder 22 and the output of the subtracter 23 according to the comparison result of the second step. The DAC 14 decodes the output of the MUX 24 and then switches the connection in the DAC to change the output Vr. This process requires a decoding time required to decode the output of the MUX 24 and a DAC settling time until the DAC output Vr is stabilized. The DAC settling time is related to the slew rate of the amplifier in the case of a DAC using a ladder resistor, and is related to the charge transfer time determined by the capacitance and the resistance in the case of a charge sharing type DAC. Since the amount of change in the DAC output Vr is larger in the previous step, the DAC settling time is longer in the first step and gradually shorter. Thereafter, the same operation is repeated.

  Non-Patent Documents 1 and 2 propose a method that allows a settling error due to a comparison by shortening the cycle time and performing a comparison when the output of the DA converter is insufficient. is doing. In this method, the number of steps is larger than that of the binary algorithm, but the cycle time is shortened, so that the overall speed can be increased.

  Non-Patent Document 3 describes a redundancy algorithm in a SAR ADC using a DA converter.

F.Kuttner “A 1.2V 10b 20MS / S Non-Binary Successive Approximation ADC in 0.13um CMOS” Tech. Digest of ISSCC (Feb. 2002) M. Hesener, T. Eichler, A. Hanneberg, D. Herbison, F. Kuttner, H. Wenske “A 14b 40MS / s Redundant SAR ADC with 480MHz Clock in 0.13um CMOS” Tech. Digest of ISSCC (Feb. 2007) T.Ogawa, H.Kobayashi, M.Hotta, Y.Takahashi, H.San, N.Takai “SAR ADC Algorithm with Redundancy”, IEEE Asia Pacific Conference on Circuits and Systems, Macao, pp.268-271, Dec. 2008

  An AD converter using a redundant algorithm (non-binary algorithm) has been proposed, but the test method is not particularly proposed, and the same test method as that for an AD converter using a binary algorithm is applied. It is thought. That is, the voltage of the input signal to the AD converter is changed by the minimum level over the input range, and it is detected whether the AD conversion for the input signal voltage at each level is a correct value. Usually, such a test is performed while changing the operating environment such as voltage and temperature, and it is confirmed that correct AD conversion values can be obtained under all conditions.

  The AD conversion value is determined by a series of determination result sequences of a plurality of steps. However, according to the redundancy algorithm, the same AD conversion value may be obtained by a plurality of different series of determination result sequences. When performing an operation test of an AD converter using a redundancy algorithm, it is desirable to test the operation of all columns of a series of different determination result sequences.

  However, in the above test, only the operation of one column among a plurality of different judgment result sequences is tested. When testing with different operating environments as described above, it may be possible to test the operation of different columns, but it is not known which column of a plurality of different judgment result sequences was tested. .

  The DAC settling time shown in FIG. 5 varies with voltage, temperature, and the like. For this reason, if the comparison is performed when the DAC output Vr is sufficiently settled, a correct comparison is performed. However, if the comparison is performed before the DAC output Vr is sufficiently settled, an error occurs in the comparison result. Can happen. However, in the case of an AD converter using a redundant algorithm, a correct AD conversion value may be obtained even if an error occurs in the comparison result in the middle. In such a case, an error occurs in the comparison result in the middle. I can't know. As described above, by using the redundancy algorithm, a correct AD conversion value can be obtained, but it is not known which column of a plurality of different judgment result columns has been operated.

  A scan circuit is known as a method for testing the internal operation of an integrated circuit. The scan circuit is provided with a flip-flop (FF) that latches or sets the state of each part in the circuit, a signal path that outputs the state latched by the FF to the outside, and operates after setting the circuit to a predetermined state. This is a circuit for outputting the latched operation state to the outside. The scan circuit makes it possible to check the operation state in the circuit. The FF in the circuit may be used as the FF of the scan circuit. If an AD converter using a redundancy algorithm is provided with a scan circuit, it is possible to check the operation state in the circuit and know which column of a plurality of different judgment result sequences has been operated. is there.

However, when a scan circuit is provided in an AD converter using a redundancy algorithm, it is necessary to provide a MUX that switches input / output for each of many FFs that latch the value of each bit of the register 25, and to provide wiring between them. The problem that the circuit scale becomes large occurs.
The successive approximation ADC is desired to have a small chip area and low power consumption, and in reality, a scan circuit cannot be provided.

  An object of the present invention is to enable an AD converter using a redundancy algorithm to test the operation of all of a plurality of different judgment result sequences by simply adding a simple circuit. .

  In order to solve the above problem, the successive approximation analog-digital converter (ADC) of the present invention inverts the judgment result of the comparator input to the successive approximation control circuit in a predetermined step during the operation of the ADC. After the determination operation is generated, the operation is further continued. For this reason, the ADC has a determination result input circuit that switches whether the determination result of the comparator or the inversion of the determination result is input to the successive approximation control circuit.

  That is, an analog-digital converter operation test method according to the present invention includes a digital-analog converter that outputs a reference analog signal according to an n-bit digital signal, a comparator that compares an input analog signal with a reference analog signal, A successive approximation control circuit that changes the value of the n-bit digital signal in M (n <M) steps so that the reference analog signal approaches the input analog signal based on the comparison result of the comparator, The comparison control circuit is an operation test method for an analog-to-digital converter that changes the value of an n-bit digital signal according to a redundancy conversion algorithm, and operates the analog-to-digital converter by inputting a predetermined voltage signal as an input analog signal. During the operation, the judgment result of the comparator input to the successive approximation control circuit is inverted at a predetermined step, and an erroneous judgment operation is performed. Control to generate, acquire the conversion result of the predetermined voltage signal by the analog-digital converter, compare the acquired conversion result with the digital value corresponding to the predetermined voltage signal, and normalize based on the comparison result It is determined whether or not the operation.

  The analog-to-digital converter of the present invention includes a digital-to-analog converter that outputs a reference analog signal according to an n-bit digital signal, a comparator that compares an input analog signal with a reference analog signal, and a comparison of the comparators. A successive approximation control circuit that changes the value of the n-bit digital signal in M (n <M) steps so that the reference analog signal approaches the input analog signal based on the result. , An analog-to-digital converter that changes the value of an n-bit digital signal in accordance with a redundancy conversion algorithm, and a determination to switch whether to input a determination result of the comparator or an inversion of the determination result to the successive approximation control circuit It has a result input circuit.

  The relationship between the level of the input signal that can be corrected by the redundancy algorithm and the step in which the error occurs is determined according to the redundancy algorithm. Therefore, the judgment result of the comparator input to the successive approximation control circuit is inverted under correctable conditions. An erroneous determination operation occurs.

  In addition, it is possible to change the state up to the step where normal operation is performed and the determination result of the comparator input to the successive approximation control circuit is inverted to generate an erroneous determination operation. In order to achieve this, it is desirable to reverse the determination result of the comparator after controlling the determination result of the comparator input to the successive approximation control circuit until the ADC is in a predetermined state until a predetermined step. Therefore, it is desirable that the determination result input circuit can be switched to input an arbitrary determination result to the successive approximation control circuit.

  The test circuit for testing the ADC of the present invention has a memory circuit for storing the relationship of the inversion step for inputting the inversion of the determination result of the comparator determined according to the test digital signal, and the test circuit for inputting as an input analog signal An input voltage generation circuit for generating a voltage signal corresponding to the digital signal, a relationship between the test digital signal stored in the storage circuit and the inversion step is read, and the test digital signal is output to the input voltage generation circuit, and the inversion step Then, the test control circuit that controls the determination result input circuit so that the inversion of the determination result of the comparator is input to the successive approximation control circuit, and the M number of steps that the analog-digital converter outputs as the conversion value And a determination circuit that determines whether the value of the n-bit digital signal matches the value of the test digital signal. The test circuit can be used as an ADC test equipment (ATE: Automatic Test Equipment), but it can also be realized by a DSP core in an SOC (System On-Chop) in which the ADC is installed. It can also be realized as a part.

  As described above, the judgment result input circuit can be switched to input an arbitrary judgment result to the successive approximation control circuit, and the judgment of the comparator to be inputted to the successive approximation control circuit until a predetermined step. When the ADC is inverted after the ADC is controlled in a predetermined state after the control of the result, the memory circuit stores the determination information before the inversion step necessary for the predetermined state for executing the inversion step. Remember.

  The ADC has a normal operation mode and a test mode. The determination result input circuit maintains a state in which the determination result of the comparator is input to the successive approximation control circuit in the normal operation mode, and in the test mode. , Make the specified input.

  The ADC of the present invention has a simple circuit configuration by adding a 2-to-1 or 4-to-1 selection circuit (multiplexer) as a determination result input circuit to the conventional ADC.

  ADVANTAGE OF THE INVENTION According to this invention, the test of AD converter which uses a redundancy algorithm becomes easy, and it can reduce test time and test cost.

FIG. 1 is a block diagram illustrating a configuration example of a conventional successive approximation ADC. FIG. 2 is a diagram for explaining the conversion operation in the successive approximation ADC. FIG. 3 is a diagram for explaining a conversion operation in a successive approximation ADC using a redundant (non-binary) conversion algorithm. FIG. 4 is a diagram showing a schematic configuration of a successive approximation ADC using a redundant conversion algorithm. FIG. 5 is a diagram illustrating a change in the output of the DAC when changing from the second step to the third step in the successive approximation ADC. FIG. 6 is a diagram illustrating a configuration of a successive approximation analog-to-digital converter (ADC) that uses the redundancy algorithm of the embodiment. FIG. 7 is a flowchart showing the test operation, where (A) shows the test operation of the embodiment, and (B) shows the test operation of the modification. FIG. 8 is a diagram illustrating an example of a DAC weight value and an allowable error range of a 4-bit 5-step redundancy (non-binary) algorithm. FIG. 9 shows the comparison result sequence before the test target, digital signal value (comparison value), input range (test value ± q _k ) of the test signal (test digital signal) in Step 1; In addition, voltages Vin1 to Vin4 of the test signal input as test signals are shown. FIG. 10 shows a comparison result string when the voltages Vin1 to Vin4 are input and the comparison result is inverted in step 1. FIG. 11 shows the comparison result sequence before the test target in Step 2, the digital signal value (comparison value), the input range of the test signal (test digital signal) (comparison value ± q _k ), In addition, voltages Vin1 to Vin4 of the test signal input as test signals are shown. FIG. 12 shows a comparison result string when the voltages Vin1 to Vin4 are input and the comparison result is inverted in step 2. FIG. 13 shows a comparison result sequence before the test target, digital signal value (comparison value), input range (test value ± q _k ) of the test signal (test digital signal) in step 3; Furthermore, voltages Vin1 to Vin8 of the test signal input as test signals are shown. FIG. 14 shows a comparison result string when the voltages Vin1 to Vin4 are input and the comparison result is inverted in step 3. FIG. 15 shows a comparison result string when the voltages Vin5 to Vin8 are input and the comparison result is inverted in step 3. FIG. 16 is a diagram showing an example of a DAC weight value and an error tolerance range of a 4-bit 6-step redundant (non-binary) algorithm. FIG. 17 shows a comparison result sequence before the test target in Step 1, a digital signal value (comparison value), an input range of the test signal (test digital signal) (comparison value ± q _k ), Furthermore, voltages Vin1 to Vin8 of the test signal input as test signals are shown. FIG. 18 shows a comparison result string when the voltages Vin1 to Vin4 are input and the comparison result is inverted in step 1. FIG. 19 shows a comparison result string when the voltages Vin5 to Vin8 are input and the comparison result is inverted in step 1. FIG. 20 shows a comparison result sequence before the test target in Step 2, a digital signal value (comparison value), an input range of the test signal (test digital signal) (comparison value ± q _k ), Furthermore, voltages Vin1 to Vin8 of the test signal input as test signals are shown. FIG. 21 shows a comparison result string when the voltages Vin1 to Vin4 are input and the comparison result is inverted in step 2. FIG. 22 shows a comparison result string when the voltages Vin5 to Vin8 are input and the comparison result is inverted in step 2. FIG. 23 shows a comparison result string before the test target, digital signal value (comparison value), input range (test value ± q _k ) of the test signal (test digital signal) in step 3; Furthermore, voltages Vin1 to Vin16 of test signals input as test signals are shown. FIG. 24 shows a comparison result string when the voltages Vin1 to Vin4 are input and the comparison result is inverted in step 3. FIG. 25 shows a comparison result string when the voltages Vin5 to Vin8 are input and the comparison result is inverted in step 3. FIG. 26 shows a comparison result string when the voltages Vin9 to Vin12 are input and the comparison result is inverted in step 3. FIG. 27 shows a comparison result string when the voltages Vin13 to Vin16 are input and the comparison result is inverted in step 3. FIG. 28 shows a comparison result string before the test target, digital signal value (comparison value), input range (test value ± q _k ) of the test signal (test digital signal) in step 4; Indicates. FIG. 29 shows the voltages Vin1 to Vin16 of the test signal input as the test signal in Step 4. FIG. 30 shows a comparison result string when the voltages Vin1 to Vin4 are input and the comparison result is inverted in step 4. FIG. 31 shows a comparison result string when the voltages Vin5 to Vin8 are input and the comparison result is inverted in step 4. FIG. 32 shows a comparison result string when the voltages Vin9 to Vin12 are input and the comparison result is inverted in step 4. FIG. 33 shows a comparison result string when the voltages Vin13 to Vin16 are input and the comparison result is inverted in step 4.

  FIG. 6 is a diagram illustrating a configuration of a successive approximation analog-to-digital converter (ADC) that uses the redundancy algorithm of the embodiment.

  As shown in FIG. 6, the ADC of the embodiment is provided with a 2-bit (4-to-1 selection) multiplexer (MUX) 41 in a portion for inputting the comparison result of the comparator 12 to the MUX 24, and a test circuit. Unlike the conventional example shown in FIG. 4, the other parts are the same in that 50 is provided. The test circuit 50 can be used as an ADC test apparatus (ATE: Automatic Test Equipment), but can also be realized by a DSP core in an SOC (System On-Chop) in which the ADC is mounted. is there. In addition, when it is allowed to increase the circuit scale of the ADC, it can be realized as a part of the ADC. In the following description, the test circuit 50 will be described as being realized as an ATE.

  The multiplexer (MUX) 41 has four inputs, and each outputs an output signal (comparison result) of the input comparator 12, a signal obtained by inverting the output of the input comparator 12 by the inverter 42 (inverted comparison result), “0”. "And" 1 "are input, and one of the four inputs is selected and output in accordance with the 2-bit selection signal SEL from the test circuit 50. The output of the MUX 41 is input to the MUX 24 as a comparison result. Here, the output signal (comparison result) of the input comparator 12 when SEL = 0, and the signal (inverted comparison result) obtained by inverting the output of the input comparator 12 by the inverter 42 when SEL = 1 is “0” when SEL = 2. ", SEL = 3 and" 1 "is selected.

  The test circuit 50 changes the voltage of the input signal to the AD converter, which is conventionally performed by a normal ADC, by a minimum level over the input range, and detects whether the AD conversion for each level of the input signal voltage is a correct value. It shall have a function to execute the test to be performed. Therefore, the circuit element described below can be realized by using a circuit element for realizing a conventional function.

  In addition, it is desirable to perform an operation test of a plurality of different series of determination result sequences by using a redundancy algorithm described below for those determined as non-defective products in the above-described normal test.

  The test circuit 50 includes a ROM 51, a test control circuit 52, a DAC 53, and a coincidence detection circuit 54. The ROM 51 stores the relationship of the inversion step for inputting the inversion of the determination result of the comparator, which is determined according to a test digital signal, which will be described later, and the determination information before the inversion step necessary for setting the inversion step to a predetermined state. To do. The DAC 53 generates a voltage signal corresponding to the test digital signal that is input to the ADC as the input analog signal SA. The test control circuit 52 reads the relationship between the test digital signal stored in the ROM 51 and the inversion step, outputs the test digital signal to the DAC 53, and uses the MUX 41 as determination information before the inversion step until the inversion step. Therefore, after controlling to bring the ADC into a predetermined state, the successive approximation control circuit 13 is controlled to input the inversion of the determination result of the comparator 12. The coincidence detection circuit 54 determines whether the value of the n-bit digital signal determined in M steps output by the ADC as the converted value matches the value (integer value) of the test digital signal. If this determination matches, it is determined that the ADC is non-defective, and if it does not match, it is determined to be defective.

  FIG. 7 is a flowchart showing the test operation, where (A) shows the test operation of the embodiment, and (B) shows the test operation of the modification.

  As shown in FIG. 7A, when the inversion of the determination result of the comparator 12 is input to the successive approximation control circuit 13 at the k-th step, first, up to the k-1 step before the inversion step. SEL = 2 or 3 is set in accordance with the determination information, and the ADC is set in a desired state. Next, at step k, SEL = 1 is set, an incorrect comparison result is input to the MUX 24, and an operation corresponding to the erroneous determination is generated by the ADC. After the (k + 1) th step, SEL = 0 is set, a normal comparison result is input to the MUX 24, and the ADC is caused to execute AD conversion processing.

  In the example of FIG. 7A, after the ADC is set to a desired state, an erroneous determination is generated by the ADC. However, even if normal operation is performed, it is considered that the k state is in the desired state. There are cases. In that case, as shown in FIG. 7B, until the k-1th step, SEL = 0 is set, and the ADC is normally operated to obtain a desired state. Next, at step k, SEL = 1 is set, an incorrect comparison result is input to the MUX 24, and an operation corresponding to the erroneous determination is generated by the ADC. After the (k + 1) th step, SEL = 0 is set, a normal comparison result is input to the MUX 24, and the ADC is caused to execute AD conversion processing. In the test operation of FIG. 7B, the multiplexer (MUX) 41 has two inputs, and the inverter 42 outputs the output signal (comparison result) of the comparator 12 and the output of the comparator 12 respectively. An inverted signal (inverted comparison result) is input, and one of the two inputs may be selected and output according to the 1-bit selection signal SEL from the test circuit 50.

  Next, the number of columns of a plurality of different judgment result sequences by using the redundancy algorithm, that is, the number of redundant codes to be tested will be described.

For a redundant (non-binary) algorithm that determines n bits in M (n <M) steps, there are 2 ^M codes, all with 2 ^N correct patterns. Therefore, there are 2 ^M −2 ^N error correction patterns.

  The number of codes tested at each step is expressed as follows:

Number of erroneous determination correction codes at the k-th step (all determinations in the subsequent steps are correct)
= (Number in case of comparison value) × (Two types of correct answer 1 as 0 and incorrect answer 0 as 1 and incorrect judgment) × (error tolerance)
= 2 ^k-1 × 2 × q _k
Next, a method of determining a state that causes an erroneous determination in the ADC will be described.

  The k-th step comparison value Vref (k) is expressed by the following equation.

Here, p _k : weight value of DAC at k step, q _k : error tolerance range at k step, d (k): comparison result of comparator at k step (“high”: d (k) = 1, “low”: d (k) = 0).

In the k-th step, there is a 2 ^k-1 pattern comparison result sequence according to the previous comparison result.

  In the case of the k-th misjudgment correction test, the next input signal Vin is input.

_{Vref (k) -q k ≦ Vin} ≦ Vref (k) + q k
This is tested for all patterns in the comparison result sequence.

  A specific example will be described below.

  First, a case of a 4-bit 5-step redundancy (non-binary) algorithm with n = 4 and M = 5 will be described.

  FIG. 8 is a diagram illustrating an example of a DAC weight value and an error tolerance range q in a 4-bit 5-step redundancy (non-binary) algorithm. In step (STEP) 1, the initial value “8” is used, and the weight values after step 2 are “3”, “2”, “1”, and “1”. Further, the allowable error range q in steps 1 to 5 is 2, 1, 1, 0, 0. Therefore, tests are not performed for steps 4 and 5.

(A) of FIG. 9 is an input range (comparison value ± q) of the comparison result string, digital signal value (comparison value), and test signal (digital signal for test) before the test target in step 1. _k ). Since it is step 1, there is no previous comparison result column, the comparison value is “8”, and the input range is 6 to 10 (level), that is, 6.5, 7.5, 8.5, and 9.5. .

  (B) of FIG. 9 shows the voltages Vin1 to Vin4 of the above signals input as test signals.

  FIG. 10 shows a comparison result string when the voltages Vin1 to Vin4 are input and the comparison result is inverted in step 1.

  As shown in FIG. 10A, when the voltage Vin1 (9.5) is input and the comparison result is inverted in Step 1, the AD conversion value is (8-3 + 2 + 1 + 1 + 0.5-0.5 =) " 9 "and a correct AD conversion value is obtained.

  As shown in FIG. 10B, when the voltage Vin2 (8.5) is input and the comparison result is inverted in Step 1, the AD conversion value is (8−3 + 2 + 1 + 1−0.5−0.5). ) “8”, and a correct AD conversion value is obtained.

  As shown in FIG. 10C, when the voltage Vin3 (7.5) is input and the comparison result is inverted in Step 1, the AD conversion value is (8 + 3-2-1-1 + 0.5-0. 5 =) “7”, and a correct AD conversion value is obtained.

  As shown in FIG. 10D, when the voltage Vin2 (6.5) is input and the comparison result is inverted in Step 1, the AD conversion value is (8 + 3-2-1-1-0.5- 0.5 =) “6”, and a correct AD conversion value is obtained.

(A) of FIG. 11 is an input range (comparison value ± q) of the comparison result string, digital signal value (comparison value), and test signal (digital signal for test) before step 2 in step 2. _k ). In the previous comparison result column, the comparison results of step 1 are two, “1” and “0”. When the comparison result is “1”, the comparison value is (8 + 3 =) “11”, and the input range is 10 to 12, that is, 10.5 and 11.5. When the comparison result is “0”, the comparison value is (8-3 =) “5”, and the input range is 4 to 6, that is, 4.5, 5.5.

  (B) of FIG. 11 shows the voltages Vin1 to Vin4 of the above signals input as test signals.

  FIG. 12 shows a comparison result string when the voltages Vin1 to Vin4 are input and the comparison result is inverted in step 2.

  As shown in FIG. 12A, when the voltage Vin1 (11.5) is input and the comparison result is inverted in Step 2, the AD conversion value is (8 + 3−2 + 1 + 1 + 0.5−0.5 =) “ 11 ", and a correct AD conversion value is obtained.

  As shown in FIG. 12B, when the voltage Vin2 (10.5) is input and the comparison result is inverted in Step 2, the AD conversion value is (8 + 3 + 2-1-1-0.5-0. 5 =) “10”, and a correct AD conversion value is obtained.

  As shown in FIG. 12C, when the voltage Vin3 (5.5) is input and the comparison result is inverted in Step 2, the AD conversion value is (8-3-2 + 1 + 1 + 0.5-0.5 = ) “5”, and a correct AD conversion value is obtained.

  As shown in FIG. 12D, when the voltage Vin2 (4.5) is input and the comparison result is inverted in Step 2, the AD conversion value is (8-3 + 2-1-1-0.5-). 0.5 =) “4”, and a correct AD conversion value is obtained.

FIG. 13A shows an input range (comparison value ± q) of the comparison result sequence, digital signal value (comparison value), and test signal (digital signal for test) before the test in Step 3. _k ). In the previous comparison result column, the comparison results of steps 1 and 2 are four, “11”, “10”, “01”, and “00”. When the comparison result is “11”, the comparison value is (8 + 3 + 2 =) “13”, and the input range is 12 to 14, that is, 12.5 and 13.5. When the comparison result is “10”, the comparison value is (8 + 3−2 =) “9”, and the input range is 8 to 10, that is, 8.5 and 9.5. When the comparison result is “01”, the comparison value is (8−3 + 2 =) “7”, and the input range is 6 to 8, that is, 6.5 and 7.5. When the comparison result is “00”, the comparison value is (8-3-2 =) “3”, and the input range is 2 to 4, that is, 2.5 and 3.5.

  (B) of FIG. 13 shows the voltages Vin1 to Vin8 of the above-mentioned signals input as test signals.

  14 and 15 show a comparison result string when the voltages Vin1 to Vin8 are input and the comparison result is inverted in step 3. FIG.

  As shown in FIG. 14A, when the voltage Vin1 (13.5) is input and the comparison result is inverted in step 3, the AD conversion value is (8 + 3 + 2-1 + 1 + 0.5-0.5 =) " 13 ", and a correct AD conversion value is obtained.

  As shown in FIG. 14B, when the voltage Vin2 (12.5) is input and the comparison result is inverted in Step 3, the AD conversion value is (8 + 3 + 2 + 1-1-0.5-0.5 = ) “12”, and a correct AD conversion value is obtained.

  As shown in FIG. 14C, when the voltage Vin3 (9.5) is input and the comparison result is inverted in Step 3, the AD conversion value is (8 + 3-2-1 + 1 + 0.5-0.5 = ) “9” and a correct AD conversion value is obtained.

  As shown in FIG. 14D, when the voltage Vin4 (8.5) is input and the comparison result is inverted in Step 3, the AD conversion value is (8 + 3-2 + 1-1-0.5-0. 5 =) “8”, and a correct AD conversion value is obtained.

  As shown in FIG. 15A, when the voltage Vin5 (7.5) is input and the comparison result is inverted in step 3, the AD conversion value is (8-3 + 2-1 + 1 + 0.5-0.5 = ) “7”, and a correct AD conversion value is obtained.

  As shown in FIG. 15B, when the voltage Vin6 (6.5) is input and the comparison result is inverted in Step 3, the AD conversion value is (8-3 + 2 + 1-1-0.5-0. 5 =) “6”, and a correct AD conversion value is obtained.

  As shown in FIG. 15C, when the voltage Vin7 (3.5) is input and the comparison result is inverted in Step 3, the AD conversion value is (8-3-2-1 + 1 + 0.5-0. 5 =) “3”, and a correct AD conversion value is obtained.

  As shown in FIG. 15D, when the voltage Vin8 (2.5) is input and the comparison result is inverted in step 3, the AD conversion value is (8-3-2 + 1-1-0.5-). 0.5 =) “2”, and a correct AD conversion value is obtained.

  Therefore, the ROM 51 sets the previous comparison result sequence and test signal level (4 sets) shown in FIG. 9A as the case where the comparison result is inverted in Step 1, and the case where the comparison result is inverted in Step 2. The previous comparison result shown in FIG. 13A as the case where the comparison result is inverted in step 3 using the previous comparison result string and test signal level (2 + 2 = 4 sets) shown in FIG. Store column and test signal levels (4 × 2 = 8 sets).

  The test control circuit 52 reads out these data from the ROM 51 and performs necessary settings and control. For example, in the case where the comparison result is inverted in step 3 and data having a previous comparison result string of “10” and a test signal level of “9.5” is read, “9.5” is input to the DAC 53. Then, “9” (an integer value of 9.5) is set in the coincidence detection circuit 54. Then, SEL = 3 is set in step 1 and SEL = 2 is set in step 2 in accordance with the signal from the timing generation circuit 31, and the comparison value of the DAC 14 is "9". = 1 and the comparison result is inverted in step 3. Thereafter, SEL = 0 and steps 4 and 5 are executed.

  As described above, the operation of all the 16 error correction patterns of the successive approximation type ADC using the 4-bit 5-step redundancy (non-binary) algorithm can be tested.

  Next, the case of a 4-bit 6-step redundancy (non-binary) algorithm with n = 4 and M = 6 will be described.

  FIG. 16 is a diagram illustrating an example of a DAC weight value of the 4-bit 6-step redundant (non-binary) algorithm and an allowable error range q. In step (STEP) 1, the initial value “8” is used, and the weight values after step 2 are “2”, “2”, “1”, “1”, “1”. Further, the allowable error range q in steps 1 to 5 is 4, 2, 2, 1, 0, 0.

(A) of FIG. 17 is an input range (comparison value ± q) of the comparison result string, digital signal value (comparison value), and test signal (digital signal for test) before step 1 in step 1. _k ). There is no previous comparison result string, the comparison value is “8”, and the input range is 4-12.

  FIG. 17B shows the voltages Vin1 to Vin48 of the above-mentioned signal input as a test signal.

  18 and 19 show comparison result strings when the voltages Vin1 to Vin8 are input and the comparison results are inverted in Step 1. FIG. Since it is the same as the case of 4 bits and 5 steps, detailed description is omitted.

  The comparison result sequence when the comparison result is inverted in step 2 is shown in FIGS. 20 to 22, the comparison result sequence when the comparison result is inverted in step 3 is shown in FIGS. 23 to 27, and the comparison result is shown in step 4. Comparison result sequences in the case of inversion are shown in FIGS. 28 to 33, and description thereof will be omitted.

  Although the embodiments of the present invention have been described above, it goes without saying that various modifications other than those described are possible. For example, in the embodiment, the successive approximation control circuit 13 stores the weight value in the ROM 21, but the successive approximation control circuit 13 may be configured by a wired logic circuit or the like so that the ROM is not used.

  In addition, the present invention can be applied to any successive approximation ADC that uses a redundant (non-binary) algorithm.

  The present invention is used in a successive approximation AD conversion circuit using a redundant (non-binary) algorithm, a test apparatus thereof, and the like.

11 Sample hold circuit 12 Comparator 13 Successive comparison control circuit 14 DA converter 21 ROM (memory circuit)
22 Adder 23 Subtractor 24 Multiplexer 25 Register 31 Timing Generation Circuit 41 Judgment Result Input Circuit (MUX)
50 Test circuit 51 ROM
52 Test control circuit 53 DAC
54 Match detection circuit

Claims (10)

a digital-analog converter that outputs a reference analog signal in response to an n-bit digital signal; a comparator that compares an input analog signal with the reference analog signal; and the reference analog signal based on a comparison result of the comparator A successive approximation control circuit that changes the value of the n-bit digital signal in M (n <M) steps so as to approach the input analog signal, and the successive approximation control circuit includes: An analog-to-digital converter operation test method for changing a value according to a redundant conversion algorithm,
A predetermined voltage signal is input as the input analog signal to operate the analog-digital converter,
During the operation, in a predetermined step, the determination result of the comparator input to the successive approximation control circuit is inverted and control is performed so that an erroneous determination operation occurs.
Obtaining a conversion result of the predetermined voltage signal by the analog-digital converter;
A method for testing an operation of an analog-to-digital converter, wherein the obtained conversion result is compared with a digital value corresponding to the predetermined voltage signal to determine whether or not the operation is normal based on the comparison result.   2. The operation test method for an analog-digital converter according to claim 1, wherein the predetermined step for inverting the determination result of the comparator is determined in advance according to a voltage value of the predetermined voltage signal.   The control result of the comparator input to the successive approximation control circuit is controlled until the predetermined step, the analog-digital converter is brought into a predetermined state, and then the determination result of the comparator is inverted. 3. An operation test method for the analog-digital converter according to 2. a digital-to-analog converter that outputs a reference analog signal in response to an n-bit digital signal;
A comparator for comparing an input analog signal with the reference analog signal;
A successive approximation control circuit that changes the value of the n-bit digital signal in M (n <M) steps so that the reference analog signal approaches the input analog signal based on the comparison result of the comparator; Prepared,
The successive approximation control circuit is an analog-to-digital converter that changes the value of the n-bit digital signal according to a redundancy conversion algorithm,
An analog-digital converter comprising a determination result input circuit for switching whether to input a determination result of the comparator or an inversion of the determination result to the successive approximation control circuit.   The analog-digital converter according to claim 4, wherein the determination result input circuit is switchable so as to input an arbitrary determination result to the successive approximation control circuit. A storage circuit for storing a relationship of an inversion step for inputting an inversion of the determination result of the comparator determined in accordance with a test digital signal;
An input voltage generation circuit for generating a voltage signal corresponding to the test digital signal, which is input as the input analog signal;
The relationship between the test digital signal stored in the storage circuit and the inversion step is read out, and the test digital signal is output to the input voltage generation circuit. When the inversion step is reached, the comparison is performed in the successive approximation control circuit. A test control circuit for controlling the determination result input circuit so that the inversion of the determination result of the measuring instrument is input;
And a determination circuit configured to determine whether a value of the n-bit digital signal determined in M steps output by the analog-digital converter as a converted value matches a value of the test digital signal. 4. The analog-digital converter according to 4. The determination result input circuit can be switched to input an arbitrary determination result to the successive approximation control circuit,
The storage circuit stores determination information before the inversion step necessary to set a predetermined state for executing the inversion step,
The test control circuit controls the determination result input circuit according to the determination information before the inversion step until the inversion step, and sets the analog-to-digital converter to the predetermined state when executing the inversion step. The analog-to-digital converter according to claim 6. The analog-digital converter includes a normal operation mode and a test mode,
The analog-to-digital conversion according to any one of claims 4 to 7, wherein the determination result input circuit maintains a state in which the determination result of the comparator is input to the successive approximation control circuit in the normal operation mode. vessel. The operation test apparatus for an analog-digital converter according to claim 4,
A storage circuit for storing a relationship of an inversion step for inputting an inversion of the determination result of the comparator determined in accordance with a test digital signal;
An input voltage generation circuit for generating a voltage signal corresponding to the test digital signal, which is input as the input analog signal to the analog-digital converter;
The relationship between the test digital signal stored in the storage circuit and the inversion step is read out, and the test digital signal is output to the input voltage generation circuit. When the inversion step is reached, the comparison is performed in the successive approximation control circuit. A test control circuit for controlling the determination result input circuit so that the inversion of the determination result of the measuring instrument is input;
A determination circuit for determining whether the value of the n-bit digital signal determined in M steps output by the analog-digital converter as a converted value matches the value of the test digital signal; Digital converter operation test equipment. An operation test apparatus for an analog-digital converter according to claim 5,
A memory for storing the relation of the inversion step for inputting the inversion of the determination result of the comparator determined in accordance with the test digital signal and the determination information before the inversion step necessary to obtain a predetermined state for executing the inversion step. Circuit,
An input voltage generation circuit for generating a voltage signal corresponding to the test digital signal, which is input as the input analog signal to the analog-digital converter;
The relationship between the test digital signal stored in the storage circuit and the inversion step is read, the test digital signal is output to the input voltage generation circuit, and the determination result input circuit is changed to the inversion step. The determination result input is performed such that after the control is performed according to the determination information before the inversion step and the analog-digital converter is set to the predetermined state, the inversion of the determination result of the comparator is input to the successive approximation control circuit. A test control circuit for controlling the circuit;
A determination circuit for determining whether the value of the n-bit digital signal determined in M steps output by the analog-digital converter as a converted value matches the value of the test digital signal; Digital converter operation test equipment.

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