RU2172062C2 - Digital pulse-width modulator - Google Patents

Abstract

FIELD: pulse equipment, information transmitting devices, key power amplifiers. SUBSTANCE: proposed digital pulsewidth modulator incorporates rectangular pulse generator, two counters, four flip-flops, two multiplexers, pulse former, limiting circuit, reset circuit, three OR gates, four AND gates, NOT-END gate, two input, one output and sign buses. EFFECT: simplified design of modulator. 3 dwg

Description

 The invention relates to a pulse technique and can be used in information transmission devices, as well as key power amplifiers.

 The closest in technical essence is a digital modulator (see A.S. USSR N 1644371, published in BI N 15, 1991), containing a rectangular pulse generator, two counters, counting trigger, sign trigger, three elements OR, three a trigger, an inverter, six AND elements, two multiplexers, two pulse shapers, an NAND element, a limiting circuit, and a reset circuit.

 The disadvantage of the closest digital pulse width modulator is the complexity of its technical implementation.

 The essence of the invention lies in the fact that in a digital pulse-width modulator containing a square-wave pulse generator, the first and second counters, the counting trigger, the sign trigger, the first, second and third OR elements, the first and second triggers, the inverter, the first, second, third and the fourth AND elements, the first and second multiplexers, a pulse shaper, an NAND element, a limiting circuit and a reset circuit, the generator output being connected to the first inputs of the first and second OR elements and the input of the counting trigger, the output of which is inen with a counting input of the first counter, the second inputs of the first and second OR elements are connected respectively to the direct and inverse inputs of the sign trigger, the first input of which is connected to the sign bus, and the second input is connected to the inverter output, the outputs of the first and second OR elements are connected respectively to the inputs direct and reverse counting of the second counter, the bit inputs of which are connected to the output of the limiting circuit, the bit inputs of which are connected to the input signal bus, and the sign input - to the sign bus, the bit inputs of the first counter and connected to a common bus, and the output to the first input of the first AND element, the output of which is connected to the information recording inputs of the first and second counter and the inverter input, the output of the third OR element is connected to the first input of the second AND element, the direct output of the first trigger is connected to the first the input of the third OR element, and the inverse output with the second input of the first and first input of the second multiplexers, the direct output of the sign trigger is connected to the third inputs of the first and second multiplexers, the outputs of which are connected to the first and second inputs the odes of the AND-NOT element and the first inputs of the third and fourth AND elements, respectively, the output of the AND-NOT element is connected to the first input of the second trigger, the inverse output of which is connected to the second inputs of the third and fourth AND elements, the output of the reset circuit is connected to the second inputs of the first AND element and the second trigger, the output of the second counter is connected to the second input of the third element OR, the output of which is connected to the first input of the first trigger, the output of the first element And is connected to the second inputs of the second element And and the first trigger ra, direct output of which is connected to a first input of a first and a second input of the second multiplexer, the output of the second AND element is connected to the input of the pulse shaper, the output of which is connected to fourth inputs of the first and second multiplexers.

 Significant differences are expressed in a new set of connections between the elements of the device. The specified set of connections allows us to simplify the design of a digital pulse-width modulator.

 In FIG. 1 is a functional diagram of a digital modulator, FIG. 2 is a functional diagram of a restriction circuit; FIG. 3 - time diagrams of the operation of the device.

 The digital pulse-width modulator (Fig. 1) contains a rectangular pulse generator 1, counters 2 and 3, a counting trigger 4, a sign trigger 5, elements 6, 7 and 8 OR, triggers 9 and 10, an inverter 11, elements 12, 13, 14 and 15 And, multiplexers 16 and 17, pulse shaper 18, NAND element 19, limiting circuit 20, reset circuit 21, output buses 22 and 23, input bus 24, sign bus 25. The output of the rectangular pulse generator 1 is connected to the first inputs of the OR elements 6 and 7, as well as to the input of the counting trigger 4. The output of the counting trigger 4 is connected to the counting input of the counter 2, the bit inputs of which are connected to a common bus. The second inputs of the elements 6 and 7 OR are connected respectively to the direct and inverse outputs of the trigger 5 character, the first input of which is connected to the output of the inverter 11, and the second input is connected to the bus 25 of the character. The outputs of the elements 6 and 7 OR are connected respectively to the inputs of the forward and reverse counts of the counter 3, the bit inputs of which are connected to the output of the limiting circuit 20. The discharge inputs of the restriction circuit 20 are connected to the input bus 24, and the sign input is connected to the sign bus 25. The output of the counter 2 is connected to the first input of the element 12 I. The output of the element 8 OR is connected to the first input of the element 13 I. The direct output of the trigger 9 is connected to the first input of the element 8 OR, the first input of the multiplexer 16 and the second input of the multiplexer 17. The inverse output of the trigger 9 is connected with the first input of the multiplexer 17 and the second input of the multiplexer 16. The direct output of the sign trigger is connected to the third inputs of the multiplexers 16 and 17, the outputs of which are connected to the first and second inputs of the element 19 AND NOT and the first inputs of the elements 14 and 15 AND, respectively. The output of element 19 is NOT connected to the first input of trigger 10, the inverse output of which is connected to the second inputs of elements 14 and 15 I. The output of the reset circuit is connected to the second inputs of element 12 and trigger 10. The output of counter 3 is connected to the second input of element 8 OR . The output of the element 12 AND is connected to the input of the inverter 11, as well as to the inputs of recording information of the counters 2 and 3 and the second inputs of the trigger 9 and the element 13 I. The output of the element 13 And is connected to the input of the pulse shaper 18, the output of which is connected to the fourth inputs of the multiplexers 16 and 17. The outputs of the elements 14 and 15 And are connected respectively with the output buses 22 and 23.

 The rectangular pulse generator 1 can be performed, for example, on a 155 LA3 chip with quartz stabilization or with a timing capacitor. Counters 2 and 3, for example, on K555IE7 microcircuits, counting trigger 4, sign 5 trigger and triggers 9 and 10 can be performed on K555TM2 microcircuits. Elements 6, 7 and 8 on the chip K555LL1, elements 12, 13, 14 and 15 on the chip K555LL1. Element 19 AND-NOT can be performed on the chip K555LA3, and the pulse shaper - K555AG3. Multiplexers can be performed on a chip K531KP2.

 The restriction circuit 20 (Fig. 2) contains, for example, a group of 26 OR elements, a group of 27 AND elements, an AND element 28, an OR element 29 and 30, an OR NOT element 31 and an inverter 32.

 Depending on the value by which the input signal should be limited, the n-bit inputs of bus 24 are divided into two groups: from 1 to (n-m) and from (n-m + 1) to n, with m <n. The first group of bits - from 1 to (n-m) is connected to the first inputs of the group of 26 OR elements, the outputs of which are connected to the first inputs of the group of 27 AND elements, the outputs of which are (n-m) the least significant bits of the output of the limiting circuit 20. The second group of bit inputs of the bus 24 - c (n-m + 1) by n - are the corresponding bits of the output of the block 20 restrictions. They are connected to the m inputs of the AND-AND element 28 and the OR element 29. The output of the element 28 AND-NOT connected to the first input of the element 30 OR, the output of which is connected to the second inputs of the group of 27 elements I. The output of the element 29 OR is connected to the first input of the element 31 OR-NOT, the second input of which is connected to the output of the inverter 32, and the output - with the second inputs of the group of 26 OR elements. The second input of the OR element 30 and the inverter input are connected to the character bus 25.

 The reset circuit 21, for example, can be made in the form of a series-connected resistor and capacitor, with the second output of the resistor connected to the power bus, and the second output of the capacitor to the common bus. The resistance terminal connected to the capacitor is the output of the reset circuit 21.

 Digital pulse width modulator operates as follows.

 After turning on the supply voltage, the reset circuit 21 generates a signal that sets the triggers 9 and 10 to its initial state, gates through the element 12 And the counters 2 and 3, and also through the inverter 11 - trigger 5 signs. In this case, the input signal, passing through the limitation circuit 20, is recorded in the direct (with a positive sign of the signal) or additional (with a negative sign of the signal) code in the counter 3, and the sign code of this signal is recorded in the trigger 5 characters.

где n - количество разрядов двоичного счетчика;
N - мантисса входного числа,
после начальной установки (стробирования) появится отрицательный импульс (фиг. 3,б).Depending on the sign of the input signal, the pulses of the generator 1 with a frequency of f ₀ (Fig. 3, a) pass either through the element 6 OR (positive sign), or the element 7 OR (negative sign) and, respectively, either enter the direct count input or counter countdown input 3. Depending on the value N of the mantissa of the input signal at the outputs of the transfer of the counter 3 after a period of time

where n is the number of bits of the binary counter;
N is the mantissa of the input number,
after the initial installation (gating), a negative pulse will appear (Fig. 3, b).

(фиг. 3,в) со счетного триггера 4 поступают на счетный вход счетчика 2. На выходе переноса счетчика 2 через промежуток времени

после начальной установки появляется отрицательный импульс (фиг. 3,г), который, пройдя через элемент 12 И, поступает на вход сброса триггера 9 и возвращает его в исходное состояние.This negative pulse from the output of the counter 3, passing through the element 8 OR, is fed to the input of the installation of the trigger 9. At the same time, on the inverse output of the trigger 9, a low level signal appears, which is fed to the first input of the multiplexer 17 and to the second input of the multiplexer 16, and on the direct the output of the trigger 6 appears a high level signal, which is fed to the first input of the multiplexer 16, the second input of the multiplexer 17 and the second input of the element 8 OR. Rectangular pulses from the generator 1 are also fed to the input of the counting trigger 4, which divides the frequency f ₀ by 2. Rectangular pulses with a frequency

(Fig. 3, c) from the counting trigger 4 go to the counting input of the counter 2. At the output of the transfer of the counter 2 after a period of time

after the initial installation, a negative pulse appears (Fig. 3, d), which, passing through the element 12 And, is fed to the reset input of trigger 9 and returns to its original state.

Элемент 13 И и формирователь 18 импульсов служат для формирования раздвижки фронтов прямой и инверсной широтно-модулированных последовательностей, что необходимо для защиты широтно-импульсного преобразователя, в составе которого предполагается работа модулятора, от сквозных токов при переключении транзисторов. Это достигается тем, что при переключении триггера 9 сигнал (фиг. 3,е) формирователя 18 импульсов блокирует работу мультиплексоров 16 и 17. При этом на выходе мультиплексоров 16 и 17, а также на выходе элементов 14 и 15 И и, соответственно, на выходных шинах 22 и 23 появляется сигнал низкого уровня длительностью равный длительности выходного импульса формирователя 18.The negative pulse from the output of counter 2 through element 12 AND gates the counters 2 and 3 and through the inverter 11 - trigger 5 signs, after which the process of generating the output signals of counters 2 and 3, trigger 9, multiplexers 16 and 17 and elements 14 and 15 And is repeated. With a positive sign of the input signal to the output of the multiplexer 16, a signal passes from the direct output of the trigger 9 (Fig. 3, e), and to the output of the multiplexer 18 - from the inverse output of the trigger 9. If the sign of the input signal is negative, the signal from the inverse output passes trigger 9, and to the output of multiplexer 18 - from the direct output of trigger 9. As a result, on the output buses 22 and 23 (Fig. 3, g, h) of a digital pulse-width modulator, for any sign of the input signal, a direct and inverse pulse-width modulated series are obtained pulses

Element 13 And and the pulse shaper 18 are used to form a sliding of the edges of the direct and inverse of the pulse-width modulated sequences, which is necessary to protect the pulse-width converter, which includes the operation of the modulator, from through currents when switching transistors. This is achieved by the fact that when the trigger 9 is switched, the signal (Fig. 3f) of the pulse shaper 18 blocks the operation of the multiplexers 16 and 17. At the same time, at the output of the multiplexers 16 and 17, as well as at the output of the elements 14 and 15 AND, respectively, output buses 22 and 23 there is a low level signal with a duration equal to the duration of the output pulse of the shaper 18.

 Element 19 AND-NOT and trigger 10 serve to protect the pulse-width converter from possible failures. When high-level signals appear simultaneously at the outputs of multiplexers 16 and 17, a low-level signal appears at the output of AND-NOT element 19, which sets a low-level signal at the output of trigger 10. When this occurs, the elements 14 and 15 are blocked, and a low level signal appears on the output buses 22 and 23 of the modulator.

 The limiting circuit 20 is intended to limit at a certain level of the input signal in order to exclude the possibility of overturning pulse width modulation.

 Thus, the proposed digital pulse width modulator provides the same functions as the prototype, with a significant simplification of the device.

Claims (1)

 A digital pulse-width modulator comprising a square-wave pulse generator, first and second counters, counting trigger, sign trigger, first, second and third elements OR, first and second triggers, inverter, first, second, third and fourth elements And, first and second multiplexers, pulse shaper, AND element - NOT, a limiting circuit and a reset circuit, and the output of the rectangular pulse generator is connected to the first inputs of the first and second OR elements and the input of the counting trigger, the output of which is connected to the counting input ohm of the first counter, the second inputs of the first and second OR elements are connected respectively to the direct and inverse outputs of the sign trigger, the first input of which is connected to the sign bus, and the second input to the inverter output, the outputs of the first and second OR elements are connected respectively to the inputs of direct and reverse accounts of the second counter, the bit inputs of which are connected to the output of the restriction circuit, the bit inputs of which are connected to the input signal bus, and the sign input is connected to the sign bus, the bit inputs of the first counter are connected to the common bus, and the output is with the first input of the first AND element, whose output is connected to the information recording inputs of the first and second counters and the inverter input, the output of the third OR element is connected to the first input of the second AND element, the direct output of the first trigger is connected to the first input of the third OR element and the inverse output is with the second input of the first and first input of the second multiplexers, the direct output of the sign trigger is connected to the third inputs of the first and second multiplexers, the outputs of which are connected to the first and second inputs of the AND element - E and the first inputs of the third and fourth elements AND, respectively, the output of the element AND is NOT connected to the first input of the second trigger, the inverse output of which is connected to the second inputs of the third and fourth elements AND, the output of the collection circuit is connected to the second inputs of the first element And and the second trigger, the outputs of the third and fourth elements AND are connected respectively to the output buses, characterized in that the output of the second counter is connected to the second input of the third OR element, the output of which is connected to the first input of the first trigger RA, the input of the first element And is connected to the second inputs of the second element And the first trigger, the direct output of which is connected to the first input of the first and second input of the second multiplexers, the output of the second element And is connected to the input of the pulse shaper, the output of which is connected to the fourth inputs of the first and second multiplexers.

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