RU1827674C - Memory address computing unit - Google Patents

Abstract

The present invention relates to computer technology, in particular to memory address generation devices, and can be used in computer channels to generate information addresses. The essence of the invention lies in the fact that by including an array size and a second decoder in the register device, it is possible to independently control the number and size of arrays involved in the process of merging or stratifying arrays. This makes it possible to reduce the time for solving problems requiring the performance of the indicated procedures, and thereby increase the actual performance of the computer that includes this device. 1 ill.

Description

The invention relates to digital computing, in particular to devices for generating a computer memory address, and can be used in computer channels to form a memory access

The purpose of the invention is to expand the functionality of the device due to the possibility of stratification of the received array of information and fetching out arrays of information with the possibility of independent change in the number and size of the arrays of information.

The drawing shows a functional diagram of the device.

The device contains an n-bit address switch 1 (KA), an n-bit address register 2 (PA), n one-bit adders (I), of which the main 3 adders 3 make up the first group, and Cn - m) of the adders 4 constitute the second group, address modification register 5 (PM). the first decoder 6 (DSH1), the trigger 7 mode (TP), the register 8 size of the array (PP), the second decoder 9 (DSH2), (t -1) elements 10 and switch 11 transfers (KP).

The information inputs of the device are connected to the information inputs of the registers 5, 7 and the first information inputs of the switch 1, the outputs of which are connected to the information inputs of the register 2, the outputs of which are connected to the outputs 13 of the device and the first inputs of the adders 3, 4, the outputs of the sums of which are connected to the second information the inputs of the switch 1. The clock input 14 of the device is connected to the clock inputs of the registers 2, 5, 8. From the first to the sixth control inputs 15 of the device are connected to the control inputs of the switch 1, register 2, reg tra 5, a zero setting input of the flip-flop 7, input for setting the latch in unit 7, a control input regisl

with

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page 8, respectively, the outputs of the register 5 are connected to the information inputs of the decoder b, the outputs of which are connected to the second inputs of the adders 3. The direct output of the trigger 7 is connected to the blocking inputs of the decoders 6.9 and switch 11. The outputs of the register 8 are connected to the control inputs of the switch 11 and information inputs of the decoder 9, the outputs of which are connected to the first inputs of the elements And 10, the second inputs of which are connected to the outputs of transfers following the number of adders 3 and the following information inputs of the commutator ator 11, the output of which is connected to the third input of the youngest of the adders 4. The transfer output of the eldest from the adders 3 is connected to the first information input of the switch 11. The outputs of the elements M 10 are connected to the third inputs of the adders 3 corresponding in number. The outputs of the transfers of the adders 4 are connected to third inputs of the previous adders by number. The second input of the youngest of the adders 4 is connected to the inverse output of the trigger 7, the second inputs of the remaining adders 4 are connected to the logical zero bus.

The implementation of the proposed device is possible using standard elements of computer technology.

The device operates as follows.

Before starting work, with the help of control signals supplied to the inputs 15 of the device and a clock signal supplied to the input 14 of the device, information is transferred to all the registers to the inputs 12 of the device. After that, the initial address of the memory is set at the outputs 13 of the device and the device expects signals of its modification.

If the trigger 7 is in the O state, then the signal corresponding to the level of the logical unit from the inverse arm of the trigger is fed to the second input of the least significant bit of the adder. At the outputs of the adder, another address is formed, increased by one compared to the initial one. Since the download is finished, the switch 1 is configured to work on the second inputs and passes the next address to the inputs of register 2. When the subscriber’s request is processed, the information is exchanged by accessing the memory at the address set on the outputs 13 of the device, and at the same time And one clock cycle at the second input from the group of control inputs 15 to the control input of register 2, a signal is allowed and received. Near

to the clock, the next address is received in register 2, from the outputs of which it goes to the outputs 13 of the device and to the inputs of adders 3, 4 for the next modification. When servicing another subscriber request, the process repeats. The decoders 6, 9 and the switch 11 are blocked by the output signal of the trigger 7 and do not participate in the work.

If trigger 7 is set to one, then a signal corresponding to the logic zero level is supplied to the second input of the least significant bit of the adder. However, decoders 6, 9 and switch 11 are unlocked. As a result, only the older part of the address (bits from 1 to t) can be modified, and the younger part of it will remain unchanged until a transfer is generated to which switch 11 is configured. The type involved in the procedure is determined by the code value in the PP register. The value of the code in the PM register determines the size of the array. The difference in the values of the codes in the registers PP and PM determines the number of arrays. The value of the code in the bits of the RA register that are not involved in the modification determines the location of these arrays in memory. In the cycle of operation following the cycle in which the transfer is generated, to which switch 11 is configured, the code in the bits of the senior part involved in the modification of the address becomes zero, and the code in the minor part increases by one, the Code in the bits of the senior part, not involved in address modification, remains unchanged throughout the procedure. In the following clock cycles, only the older part of the address will be modified again, and the younger will remain unchanged until the transfer defined by the code in the Pp register is generated again. Thus, in the process of exchanging with the subscriber, the array of information received from it will be stratified into several arrays, the size of which is determined by the code stored in register 5, and the quantity by the difference of the codes stored in registers 8 and 5. When the information is sent to the subscriber, merging of information arrays stored in the memory occurs.

Claims (1)

SUMMARY OF THE INVENTION A memory address generating device comprising an address switch, an address register, n adders, an address modification register, a decoder and a mode trigger, the information input of the device being connected to the information input of the modification register and the first information input of the address switch which is connected to the information input of the address register, the outputs of which are bitwise connected to the outputs of the device and the inputs of the first terms of all adders, the outputs of the sums of which are connected to the bits of the second information input of the address switch, the clock input of the device is connected to the clocks of the address register and address modification register, setup input, reception enable input, address modification input, installation input to O, installation input to 1 devices are connected respectively to the control input of the address switch, input the mode of the address register, the input of the mode of the register of modification, the input of the setting in O of the mode trigger and the input of setting 1 in this trigger, respectively, the output of the register of address modification is connected to the information input of the decoder, the output of the 1st digit of which is connected to the input of the second term of the 1st ( Where I e 1t) totalizer, transfer output a-th (where a m + 1n) the adder is connected to a transfer input (a - 1} -th adder, characterized in that, in order to expand the functionality of the device by stratifying the received information array and if the information arrays are issued if it is possible to independently change the number and size of the information arrays, an array size register is entered into it, a second decoder, a group of AND elements, and an m-input transfer switch, the information inputs of the device being connected to the information inputs of an array-sized register, the output of which is connected to the control the input input of the portable switch and the information input of the second decoder, the output of which is 0 din with the first inputs of the elements of the And group, the second input of the b-th (where b 1, ..., m-1) element of the And group is connected to the transfer output of the (b + 1) -th adder and (b + 1) -m switch information input house 5 transfers, the output of which is connected to the transfer input of the nth adder, the input of the second term of which is connected to the inverse output of the mode trigger, the second inputs m + 1 through n - 1 of the adders are connected to 0 by the input of the logic zero of the device, the transfer output of the first adder is connected to the input of the first bit of the transfer switch, the outputs of 1 elements and groups are connected respectively to the inputs of the 5 transfer of 1 adders, the device sync input is connected to the size register sync input, the mode input of which is connected with the input of the size of the device array, the direct output of the mode trigger is connected 0 with blocking inputs of the first and second decoders and transfer switch.