RU1802400C - Device for formation of pulse sequences - Google Patents

Description

The invention relates to a pulsed technique and can be used in radar and sonar when measuring the coordinates of objects, as well as in communication systems with noise-like signals.

 The aim of the invention is to expand the functionality of the device by increasing the range of delays.

The drawing shows the functional | electrical circuit of a pulse train.

The device contains a generator 1 of counting pulses, the first 2 and second 3 pulse counters. Comparison unit 4, inverter 5,. I-OR 6, first 7 and second 8 clock generators, first 9 and three 10 discrete pulse sequence generators, trigger 11 and elements 12, 13, 14, 15. 16 AND WITH RELATED CONNECTIONS.

An apparatus for generating pulse sequences operates as follows.

In the counter 2, by any of the known methods, a certain number K is written before starting work, which determines the set delay value in the clock cycles of the generator 1. The counter 3 is reset, the trigger 11 is in the zero state. Clock pulses from the output of the generator 1 are fed to the second inputs of the elements And 12 and AND-OR 6, as well as the clock input of the generator 9. At the output of the element And 12, clock pulses do not pass, because the first input receives zero potential from the output of trigger 11. Since the unit potential arrives at the first input of the AND-OR 6 element from the inverter 5 output, pulses from the output of generator 1 through the AND-OR 6 element go to the clock input of the discrete pulse generator 10 sequences, which stops at the moment when the output of the shaper 8 fixation of the initial

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The phases of the generated discrete sequence produce a signal which is inverted by the inverter 5 and locks the second input of the AND-OR element 6. Thus, the device is automatically prepared for operation. At the same time, the signal from the output of the driver 8 is fed to the second input of the element And 13. Therefore, as soon as the initial phases of the generators 10 and 9 coincide, the output of the generator 7 of the clock signal displays a unit potential, which sets the trigger 11 to the single state through the element And 13. The unit potential from the output of the trigger 11 goes to the zero input of the element And 14 and to the first input of the element And 12, which ensures the passage of pulses from the output of the generator 1 through the element And 12 to the counting input of the counter 3, which sums the counting pulses arriving at its input to those since until the states of the counters 2 and 3 coincide, which is fixed using the comparison unit 4, the output signal of which through the second input of the element And 14 resets the counter 3. puts the trigger 11 in the zero state, and also goes to the fourth input of the And OR 6. Therefore, the output of the generator 1 through the third input of the AND-OR 6 element to the generator 10 of discrete pulse sequences receives a clock pulse. The generator 10 exits the initial state. The potential at the output of the driver 8 for fixing the initial phase of the sequence disappears, the unit potential arrives at the first input of the AND-OR element b from the inverter 5 output and the discrete pulse sequences from the output of generator 1 go to the clock input of the generator 2 through 2-AND-OR b clock pulses. The generator 10 generates a pulse sequence delayed by K clocks

From the output of the element And 15, the pulses are fed to the input of the counter 2 to increase, and from the output of the element And 16 to reduce its content. This makes it easy to adjust the delay.

Thus, in the counter 2, any number K can be written, including more in its value of the duration of the un hold sequence, and the generation of the delayed sequence will begin only after the K cycles of generating the un hold sequence.

The technical and economic efficiency of the present invention consists in expanding the functionality by providing a delay value for the pulse sequences that can be longer than the duration (in cycles) of the delayed pulse sequence, thereby providing, for example, a longer measuring distance of the coordinates of the object in the radio - and sonar.

The device is invariant to the structure of the generated delayed sequence and to the number of its code features and

generates delayed multilevel or multiphase or multiphase discrete sequences with a large period of arbitrary periodicity and structure, providing constant self-control of the delay value and automatic restoration of a given delay in case of random failures, and adjusts the delay.

The reliability of achieving the goal is confirmed by the description of the operation of the device.

Claims (1)

SUMMARY OF THE INVENTION An apparatus for generating pulse sequences, comprising a counting pulse generator, first and second pulse counters, a comparison unit, an inverter, an AND-OR element, first and second formatter and clock pulses, first and second discrete generators pulse sequences, the output of the counter pulse generator is connected to the clock input of the first generator of discrete pulse sequences and to the second and third inputs of the element OR, the output of which is connected to the clock input of the second generator of discrete pulse sequences, the first outputs of which are connected through a second shaper of the clock pulses and the inverter to the first input of the AND-OR element, the first outputs of the first generator of discrete pulse sequences connected to the inputs of the first driver clock pulses, the information outputs of the first pulse counter are connected to the first inputs of the comparison unit, the output of which is connected to the fourth input of the AND-OR element, the second output of the first a discrete pulse generator is an output of unobstructed discrete sequences, and a second output of a second discrete pulse generator is an output of delayed discrete sequences, characterized in that what. in order to expand the functionality, a trigger is introduced into it, the first, second, third, fourth and fifth elements of I. The trigger output is connected to the first input of the third element And and through the first element And, the second input of which is connected to the output of the counting pulse generator , connected to the first input of the second pulse counter, the output of the first Sync pulse generator through the And element, the second input of the second element And connected to the output of the second synchronizer, connected to the first trigger input, the second input is third his; And element is connected to the first inputs of the fourth and fifth elements And, to the second 0 the trigger input and the output of the comparison unit, the output of the third AND element is connected to the second input of the second pulse counter, the outputs of the fourth and fifth elements AND are connected to the first and second inputs of the first pulse counter, and the second inputs of the fourth and fifth elements AND are connected to the first and the second inputs of the first pulse counter, and the second inputs of the fourth and fifth elements are connected to the first and second mismatch inputs.