RU1798900C - Pulse signal generator - Google Patents

Abstract

The invention relates to a pulse technique and is intended for use in input logic circuits of broadband time pulse converters. The device comprises a limiter amplifier, a control unit, a clock pulse generator, two reversible counters, two decoders, and a trigger. The control unit contains a counting trigger, four elements I. 4 ill.

Description

The invention relates to a pulsed technique and is intended for use in input logic circuits of broadband time pulsed converters and measuring devices, frequency meters, phase meters, as well as signal detectors against the background of broadband interference.

The purpose of the invention is to improve noise immunity with a limited rate of change of the frequency of the input signal.

Fig. 1 is a structural diagram of a pulse signal driver. Fig. 2 is a timing diagram illustrating the operation of the device without noise: Fig. 2a is an input signal; 26 is a signal at input 2 of the control unit; 2c is the code in the first reverse counter; 2d - code in the second reverse counter; 2d - trigger output signal. Fig. 3 shows the timing diagrams of the signals at the corresponding points of the device 2 under the action of a mixture of signal and noise at the input of the amplifier-limiter 1; Fig.ZZ - input signal; 36 - signal on input 2 of the control unit; Sv - code in the first reverse counter; Zg is the code in the second reverse counter; Zd - trigger output signal. Figure 4 presents the timing diagrams

signals at the corresponding points of the proposed device when acting at its input the same mixture of signal and noise, as in Fig.Z; on figa - input signal; Fig. 46 is a signal on input 2 of the control unit; 4c - code in the first reversible counter; Fig.4g - code in the second reverse counter; figd - the output signal of the trigger.

The proposed device (figure 1) contains an amplifier-limiter (UO) 1, control unit 2 (control unit), a clock generator 3 (G), reversible counters (PC) 4 and 5, decoders (DS) 6 and 7, a trigger ( T) 8. The control unit consists of a counting trigger (CT) 9 and four AND elements (10-13). Moreover, the output of the counting trigger 9 is connected to the first inputs of the first and second elements And 10 and 11, the second input of the first of which is connected to the first input of the third element And 12 and to the first output of the amplifier-limiter 1, the input of which is connected to the input bus, the second output with the second input of the second element And 11 and with the first input of the fourth element And 13, the second input of which is connected to the output of the pulse generator 3, with the input of the counting trigger 9 and with the second input

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the third element And 12, and the outputs of the first. and the second elements And 10 and 11 are connected to the inputs of the summation of the first and second reverse counters 4 and 5, respectively, the subtraction inputs of which are connected to the outputs of the fourth and third elements And 13 and 12, respectively, the outputs are through the first and second decoders 6 and 7, respectively, with S- and R-inputs of trigger 8, the direct output of which is connected to the output bus 15 and to the third input of the third element And 12, the inverse output is the third input of the fourth element And 13.

The device operates as follows, the input harmonic signal is fed to the amplifier-limiter 1, where it is converted into a sequence of rectangular pulses corresponding in duration to half the period of the signal. These pulses from the output of the amplifier-limiter 1 and the pulses from the outputs of the trigger 8 through the control unit 2 set the operation mode of the first 4 and second 5 reverse counters in such a way that during the action of the negative half-wave of the input signal one reverse counter, for example, the first 4 operates to sum , second 5, in the presence of a logical unit at the corresponding output of trigger 8, for subtraction; During the operation of the positive half-wave of the signal, vice versa. The read pulses with a frequency f0 are supplied to the control unit 2 from the clock generator 3, where, using the counting trigger 9, a sequence of counting pulses with frequencies f0 / 2 is formed.

Pulses with a frequency of W2 through the first 10 and second 11 elements of And arrive at the inputs of the summation of the first 4 and second 5 reverse counters, and pulses with a frequency of f0 through the fourth 13 and third 12 elements of And arrive at the inputs of the subtraction of the reverse counters 4 and 5. Thus The accumulation of code by reversing counters 4 and 5 is twice as slow as subtracting.

The decoding of the zero state, for example, by the decoder 7 sets the trigger 8 to the state of logical unit and, thus, allows the passage of pulses with a frequency f0 through the fourth 13th element And the first 4 reverse counter and prohibits their passage through the third

12 element And on the second 5 reverse counter.

Therefore, at the next moment, it is possible to decrypt the zero state

only on the first 4 reverse counter with a decoder b, which changes the state of trigger 8 and, thus, prohibits the first 4 reverse counter to be counted as minus and allows the second to be counted as minus

5 reverse counter. Since the direction of counting of the first 4 and second 5 reverse counters is controlled via the input signal control unit 2, in the steady-state mode, the switching times

Claims (1)

trigger 8 will correspond to the extremes of the input signal. The prohibition of counting minus the corresponding reversible counter after decrypting zero at its outputs leads to faster accumulation of code in this counter when a signal mixture and broadband noise are applied to the input of the device, which significantly increases the noise immunity of the device. . The claims A pulse signal generator comprising a control unit that contains four AND elements and a counting trigger, the output of which is connected to the first inputs of the first and second AND elements, the second input of the first of which is connected to the first input of the third AND element and to the first output of the amplifier-limiter, the input of which is connected to the input bus, the second output to the second input of the second element And with the first input of the fourth element And, the second input of which is connected to the output of the pulse generator, with the input of the counting trigger and with the second input of the third element l / l, and the outputs of the first and second And elements are connected to inputs of summing, respectively, of the first and second reversible pulse counters, the subtraction inputs of which are connected to the outputs of the fourth and third elements, respectively, outputs - through respectively the first and second decoders with R- and S-inputs of the trigger, (direct output which is connected to the output bus, which means that, in order to increase noise immunity at a limited rate of change of the input signal frequency, the direct and inverse outputs of the trigger are connected to the third inputs, respectively essentially the third and fourth elements of I. (fJU & 1 T D IFig2 I GP PP Fig.Z