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NO862765D0 - PROCEDURE FOR THE MANUFACTURING OF MICROMODULES FOR COMPONENT CARDS AND PRODUCTS MANUFACTURED BY THE PROCEDURE. - Google Patents

PROCEDURE FOR THE MANUFACTURING OF MICROMODULES FOR COMPONENT CARDS AND PRODUCTS MANUFACTURED BY THE PROCEDURE.

Info

Publication number
NO862765D0
NO862765D0 NO862765A NO862765A NO862765D0 NO 862765 D0 NO862765 D0 NO 862765D0 NO 862765 A NO862765 A NO 862765A NO 862765 A NO862765 A NO 862765A NO 862765 D0 NO862765 D0 NO 862765D0
Authority
NO
Norway
Prior art keywords
procedure
micromodules
manufacturing
products manufactured
component cards
Prior art date
Application number
NO862765A
Other languages
Norwegian (no)
Other versions
NO862765L (en
Inventor
Jean Pierre Gloton
Phillippe Peres
Original Assignee
Eurotechnique Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eurotechnique Sa filed Critical Eurotechnique Sa
Publication of NO862765D0 publication Critical patent/NO862765D0/en
Publication of NO862765L publication Critical patent/NO862765L/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Paper (AREA)
  • Inspection Of Paper Currency And Valuable Securities (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
NO862765A 1985-07-12 1986-07-08 PROCEDURE FOR THE MANUFACTURING OF MICROMODULES FOR COMPONENT CARDS AND PRODUCTS MANUFACTURED BY THE PROCEDURE. NO862765L (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8510719A FR2584862B1 (en) 1985-07-12 1985-07-12 PROCESS FOR THE CONTINUOUS MANUFACTURE OF MICROMODULES FOR CARDS CONTAINING COMPONENTS, CONTINUOUS BAND OF MICROMODULES AND MICROMODULES CARRIED OUT BY SUCH A PROCESS

Publications (2)

Publication Number Publication Date
NO862765D0 true NO862765D0 (en) 1986-07-08
NO862765L NO862765L (en) 1987-01-13

Family

ID=9321252

Family Applications (1)

Application Number Title Priority Date Filing Date
NO862765A NO862765L (en) 1985-07-12 1986-07-08 PROCEDURE FOR THE MANUFACTURING OF MICROMODULES FOR COMPONENT CARDS AND PRODUCTS MANUFACTURED BY THE PROCEDURE.

Country Status (4)

Country Link
EP (1) EP0211716A1 (en)
JP (1) JPS6219496A (en)
FR (1) FR2584862B1 (en)
NO (1) NO862765L (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2632100B1 (en) * 1988-05-25 1992-02-21 Schlumberger Ind Sa PROCESS FOR PRODUCING AN ELECTRONIC MEMORY CARD AND ELECTRONIC MEMORY CARDS OBTAINED BY IMPLEMENTING SAID METHOD
EP0408904A3 (en) * 1989-07-21 1992-01-02 Motorola Inc. Surface mounting semiconductor device and method
CH686325A5 (en) * 1992-11-27 1996-02-29 Esec Sempac Sa Electronic module and chip card.
US5977613A (en) * 1996-03-07 1999-11-02 Matsushita Electronics Corporation Electronic component, method for making the same, and lead frame and mold assembly for use therein
FR2761527B1 (en) * 1997-03-25 1999-06-04 Gemplus Card Int METHOD OF MANUFACTURING CONTACTLESS CARD WITH ANTENNA CONNECTION BY WELDED WIRES
JP4537955B2 (en) * 2002-10-15 2010-09-08 ゲマルト ソシエテ アノニム Method for manufacturing a data carrier
JP4843950B2 (en) * 2005-01-27 2011-12-21 スズキ株式会社 Tilt-up regulating device for outboard motor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2985806A (en) * 1958-12-24 1961-05-23 Philco Corp Semiconductor fabrication
DE2305883A1 (en) * 1973-02-07 1974-08-15 Finsterhoelzl Rafi Elekt CIRCUIT BOARD
FR2337381A1 (en) * 1975-12-31 1977-07-29 Honeywell Bull Soc Ind PORTABLE CARD FOR ELECTRICAL SIGNAL PROCESSING SYSTEM AND PROCESS FOR MANUFACTURING THIS CARD
GB2073947B (en) * 1980-04-11 1983-12-21 Philips Electronic Associated Integrated circuit encapsulation
DE3051195C2 (en) * 1980-08-05 1997-08-28 Gao Ges Automation Org Package for integrated circuit incorporated in identity cards
JPS5947748A (en) * 1982-09-10 1984-03-17 Hitachi Ltd Lead frame for semiconductor device

Also Published As

Publication number Publication date
EP0211716A1 (en) 1987-02-25
FR2584862A1 (en) 1987-01-16
FR2584862B1 (en) 1988-05-20
NO862765L (en) 1987-01-13
JPS6219496A (en) 1987-01-28

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