NL8204050A - SIGNAL MEASURING INSTRUMENT. - Google Patents

Description

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823202 / AA / vL

Short designation: Signal measuring instrument

The invention relates to a signal measuring instrument comprising a digital one. memory chain for storing an input signal.

A digital oscilloscope such as a transition signal recorder is a signal measuring instrument that converts an analog input signal into a digital signal, stores the digital signal in a digital memory chain and converts the stored signal into an analog signal for display on a display unit such as a cathode ray tube (CRT). A logic analyzer 10 is a signal instrument that stores a digital input signal in a digital memory chain and maps the stored digital signal on a CRT. Since these signal measuring instruments comprise digital memory circuits, they can record input signals supplied before the trigger points and, in addition, the stored digital signals can be processed by a computer. Instruments of this kind are therefore very useful.

A digital oscilloscope known from practice comprises a single memory for the storage of an analog signal converted into digital form, wherein the contents of the memory can be imaged on the screen of a cathode ray tube.

However, a signal measuring instrument of this kind has the drawback that no new input signal can be recorded while displaying a previously stored input signal. The instrument is therefore not efficient to use.

Another known digital oscilloscope comprises two memories, in which in one memory the analog signal converted into digital form is stored and then the contents of this one memory are transferred to the other memory, the contents of which are displayed on the screen of a cathode ray tube can be displayed. This allows the user to store a new input signal in the first memory while observing the older input signal stored in the second memory. However, such a system has the drawback that a not negligible loss of time occurs during the transfer of the contents from one memory to another memory. This poses an objection to wanting to observe phenomena that occur at unknown times.

The object of the invention is to eliminate these drawbacks and to this end provide a signal measuring instrument comprising a memory divided into different sectors with a separate address generator for each sector. From the resp. address generators are fed under the control of a control circuit and a multiplexer address signals to the memory sectors to be able to read one memory sector while another is being described.

The object of the invention is to provide an improved signal measuring instrument with which a new input signal can be stored in a memory and at the same time a previously stored input signal can be taken from the memory chain at any arbitrary time.

The invention is elucidated with reference to the drawing. In the drawing: Fig. 1 shows a block diagram of a known signal measuring instrument, Fig. 2 shows a block diagram of a second known signal measuring instrument, Fig. 3 shows a block diagram of a preferred embodiment of the measuring instrument according to the invention, Fig. 4 shows the memory content of a memory divided into two sectors, and FIG. 5 is a timing chart for explaining the multiplexing operation.

In the known signal measuring instrument shown in Fig. 1, which is a digital oscilloscope, an analog input signal from a terminal 10 is converted by an analog-to-digital converter 12 (A / D) into a digital (parallel) signal and the output signal thus obtained is formed at the data input terminal of a memory circuit 14, which memory may be an arbitrarily accessible memory (RAM). The digital (parallel) signal from the data output terminal of the memory circuit 14 is converted into an analog signal by a digital-analog converter 16 (D / A) 8204050 ψ ~~~ -3- «# and the output signal thus obtained is fed to the vertical deflection plate of a cathode ray tube (CRT) 13. The address of the memory circuit 14 is determined by a parallel binary address signal 5 from an address generator 20, which can be formed by a programmable counter, and the write and read mode (W / R) of the memory circuit 14 is controlled by a control circuit 22, which may be constituted by a system with a microprocessor, a readable memory (ROM) for fixed software 10 (firmware), and a RAM as temporary memory. The control circuit 22 supplies a programming (preset) parallel bit signal and a load command signal to the address generator 20 and controls the horizontal circuit 24 to generate a sawtooth signal to be fed to the horizontal deflection plate of the CRT 18 in synchronization with the read operation of the memory chain 14.

The clock generator (CLK) 26 supplies a clock pulse to each block.

When the control circuit 22 supplies the write command signal (W) to the control circuit 14, the converted input signal according to the signal from 20 the address generator 20 is stored in the memory circuit 14. When the memory circuit 14 reads the command signal (R) from the control circuit 22, the signal stored in the memory circuit 14 is read in accordance with the address signal, and the horizontal circuit 24 supplies the sawtooth signal 25 in response to the command signal from the control circuit 22. Since the CRT 18 outputs the D / A converter 16 receives as a vertical signal and the sawtooth signal as a horizontal signal, the input signal is displayed on the CRT 18. The control circuit 22 can set the address generator 20 for-30 with respect to a desired address by supplying address data and the load signal to the address generator, so that the operator can perceive the desired portion of the stored signal. It is noted that in Fig. 1, a trigger circuit for determining a trigger point and a delay circuit for delaying the trigger point are omitted for clarity.

When the control circuit 22 alternately feeds the write and 8204050-4 read command signals to the memory circuit 14, the signal measuring instrument of FIG. 1 can scissorsly store the input signal and display the stored input signal. The displayed signal is the new current stored input signal because the write and read memory circuit 14 uses the same address. This known signal measuring instrument cannot record a new input signal while displaying a previously stored input signal. Therefore, the operator cannot use this instrument efficiently.

This drawback can be partly eliminated by using the known signal measuring instrument shown in Fig. 2. This instrument is similar to that of FIG. 1, so that the same blocks are used for the same blocks and only differences will be discussed. This instrument includes two memory chains, namely an acquisition memory circuit 28 and a display memory circuit 30, and two address generators, namely the acquisition address generator (AAG) 32 and the display address generator (DAG) 34. The memory chains 28-30 and the address generators 32 -34 can be of the same type as with the instrument according to fig. 1. Here, too, the trigger and delay chains are omitted for clarity.

The control circuit 22 first puts the acquisition memory circuit 28 into the write mode and the output signal from the A / D converter 12 is stored in predetermined addresses of the memory circuit 28 set by the acquisition address generator 32. After the input signal has been stored, the control circuit 22 brings the acquisition and reproduction memory circuits 28 and 30 into the read and resp. rubbing modes.

The signal addressed by the acquisition address generator 32 is fed from the memory circuit 28 to the memory circuit 30 and is stored in the memory circuit 30 in accordance with the address signal from the display address generator 34. The control circuit 22 carries the read command signal to the display memory circuit 30 after the entire signal stored in memory circuit 28 has been transferred to memory circuit 30. The signal stored in the memory circuit 30 is converted by a D / A converter 16 into an analog signal 8204050-5 and displayed on a CRT 18. When the operator wants to perceive the old input signal with the CRT 18 while recording the new input signal, the control circuit 22 feeds the write command signal to memory circuit 28 for storing the output signal from the A / D converter. The operator can thereby store the old one in the display memory circuit 30. detect input signal while recording the new input signal into the acquisition memory chain 28.

This known signal measuring instrument has the drawback that the transfer time for the transfer of the stored data from the memory circuit 28 to the memory circuit 30 cannot be ignored. Namely, phenomena may occur which have to be observed. Because these phenomena can occur during the transfer period, they could be lost for inclusion in a memory circuit and for observation on a cathode ray tube.

The known signal measuring instruments discussed above are of the transition signal recorder type, but the same situation applies to instruments of the logic analyzer type.

FIG. 3 shows a block diagram of a preferred embodiment of the measuring instrument according to the invention. In connection with the similarity of the measuring instrument of FIG. 2, the same reference numerals have been used for equivalent blocks and only the differences are explained. The memory circuit 36 has at least a dual capacity and its memory area, as shown in Fig. 4, is divided into two sectors, or first and second areas. A multiplexer (MUX) 38 selectively feeds the address signals from the acquisition and display address generators 32 and 34 to the address terminal of the memory 30 circuit 36 under the control of the control circuit 22. For the same reasons as for the instruments of FIG. 1. and 2 also here the trigger and delay chains are omitted.

To record the input signal from the A / D converter 12, the control circuit 22 puts the memory circuit 36 in the write mode and allows the multiplexer 38 to select the acquisition address generator 32. The address generator 32 provides the address signal of the first region between the address numbers "0" and "m" in the memory circuit 36 because the control circuit 22 presets the address generator 8204050-6. This causes the output of the A / D to be converter 12 is stored in the first region of the memory circuit 36. After the input signal has been stored, the control circuit 22 puts the memory circuit 36 into the write mode, 5 allows the multiplexer 38 to select the display address generator 34 and the address generator 34 to select the address signal of the first region. generate memory circuit 36. The digital output of the memory circuit 36 is converted by the D / A converter 16 into an analog signal and displayed on the CRT 18 because the horizontal circuit 24 generates the sawtooth signal in response to the command from the control circuit 22.

For recording a new input signal while displaying the old input signal stored in the first region of the memory circuit 22, the control circuit 22 supplies signals A and B (shown in Fig. 5) to the memory circuit 36 and the multiplexer 38. The "high" and "low" of the control signal A determines the read and resp. writing red.

The multiplexer 38 selects the address generator 32 and 34 when the control signal B "high" resp. is "low". For example, the frequency of the signals A and B is 800 kHz. The acquisition address generator 32 supplies the address signal corresponding to the second area, the address numbers from "n" to "n + m" of the memory circuit 36, and the display address generator 34 supplies the address signal corresponding to the first area under control of the control circuit 22. It is noted that the signals A and B are synchronized with the acquisition operation of the A / D converter 12. First, the multiplexer 38 selects the address generator 34 which supplies the address "0", and the memory circuit 36 is in the reading mode, so that the old input signal stored at 30 at the address "0" of the memory circuit 36 is read. Then, the multiplexer 38 selects the address generator 32 which generates the address "n" and the memory circuit 36 is in the write mode, the new input signal being stored in the address "n" of the memory circuit 36. Thereafter, the multiplexer 38 selects the address generator 34 which generates the address "1" and the reading mode is selected, whereby the signal stored in the address "1" of the memory circuit 36 is read.

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These operations are repeated successively until the address generator 32 and 34 have the addresses "n + m", respectively. generate "m" and the address generation cycle returns to "n" and "0". The time-sharing operation cycle explained above is repeated. The phase of the signal "A" follows later than that of the signal B due to the properties of the memory circuit 36. Since the old input signal stored in the first region of the memory circuit 36 is not transmitted, no dead time and the new input signal can be absorbed immediately after recording the old input signal. This prevents missing symptoms to be observed.

To record the new input signal, the acquisition address generator 32 supplies the address signal corresponding to the first region of the memory circuit 36 and the display address generator 34 supplies the address signal corresponding to the second region. As a result, the next new input signal is stored in the first area and the signal stored in the second area is read from the memory circuit 36 in a time-saving manner.

The embodiment according to Fig. 3 relates to a transition signal recorder, but can also be applied to a logical analyzer by removing the A / D converter 12 and the D / A converter 16. The output signal of the memory circuit 36 can be used for further processing to a computer.

As can be seen from the above, with the aid of the signal measuring instrument according to the invention a new input signal can be stored in a memory chain and at the same time a previously stored input signal 30 can be read from the memory chain.

The memory chain can be divided into four areas instead of two areas for recording two-channel input signals. Hereby two input signals can be alternately fed to the memory chain and the acquisition and display address generators can generate two address signals for the two resp. channels. The two-channel input signals can be alternately stored at the consecutive memory addresses of the 8204050.18 addresses. Additional acquisition and display address generators can be used and the multiplexer selects one of the four address generators. The memory chain can be a dynamic RAM and the address generators can generate the 5 column and row address signals. The memory chain can store other data such as trigger and marker information in additional memory areas. For this purpose, a multiplexer can be used to selectively feed the input signal and the other information to the data input terminal of the memory circuit.

8204050

Claims (1)

* * -9- CCLUSION Signal measuring instrument characterized by a digital memory with a number of addressable memory sectors; a number of address signal generators, each corresponding to a resp. memory sector; a multiplexer for selectively feeding the address signals to the memory sectors; and control means for controlling the selection of the multiplexer, the control means also controlling the write and read modes of the memory sectors such that one or more input signals can be stored in selected memory sectors, while previously stored signals from other selected memory sectors can be read. 8 2 0 A 0 5 0