NL8100806A - DIGITAL TIME BASE WITH COHERENT SPEED SWITCHING. - Google Patents

Description

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8l304o / Ti / M / vL

Short designation: Digital time base with coherent speed switching

The invention relates to a digital time base for providing sampling clock pulses.

In electronic instruments such as digital processing oscilloscopes and digitizing transitional isolose lopes, very fast analog electrical pulses are converted into digital representations to facilitate storage, decomposition and display. In general, conversion to digital representations is accomplished by sampling the analog pulses with a fixed speed and then quantizing the samples by means of an analog-to-digital converter. To obtain a sampling rate with different rates for input signals of different frequencies or transition times, a sampling clock with a number of selectable clock rates can be used. Therefore, faster signals can be sampled at a higher rate and slower signals can be sampled at a proportionately slower rate, so that a maximum amount of information can be extracted from the analog signal without exceeding the available memory space. However, when using wide pulses, where the information changes very rapidly during the rising and falling edges and changes very little or not at all during the planar parts of the pulses, it has hitherto been necessary to run the sampling clock at the highest expected rate. companies to bring in the entire waveform. This results in an inefficient use of the bay sampling chain and of memory space for the flat portions of pulses.

Particularly in radar pulse analysis, it is desirable to divide the waveform into accurate time intervals and sample the information during each interval at a rate proportional to the expected rate of change of the information within each interval. Switching between clock speeds does not occur coherently in chains known from practice, resulting in unpredictable time relationships between samples obtained at different speeds, thereby obtaining a stored and reproducible waveform of arbitrary time dimensions.

In order to overcome the aforementioned drawbacks, the invention 8100806-2- provides a digital time base which is suitable for switching from one clock speed to another coherently to generate sampling clock pulse and.

Since the time characteristics and the general shape of certain waveforms or pulses to be acquired are known, the waveform can be divided into predetermined intervals and a sampling rate proportional to the expected rate of change can be selected for each interval. the .waveform within it. interval.' If both the time intervals and the sampling rates are known, the number of samples taken at each interval can also be determined taking into account that the total number of samples to be taken over the entire waveform is limited by the maximum available waveform memory. gene space.

The digital time base sampling clock comprises a base clock 15 operating at a predetermined fixed frequency, a synchronous counter sequence, which divides the base clock rate in accordance with predetermined sampling rates, and a clock gate, which passes an output pulse of the sampling clock only at the coincidence of a counter output pacing pulse and a basic clock pulse.

The predetermined sampling rates and corresponding number of samples are stored in a memory. A counter counts sampling clock output pulses, and when the number of counted pulses corresponds to the stored number for a given sampling rate, the next sample rate and the corresponding number of samples are selected. This selection is made substantially simultaneously with the last sample clock output pulse, so that the synchronous counter sequence a pulse counter for the appearance of the next base clock pulse is conditioned by the new information. Switching from one sampling rate to the other during the waveform acquisition is therefore coherent because no unpredictable or unknown time windows between the sampling clock pulse and occur.

The invention provides a digital time base with associated rate switching, which is to that end characterized by means for supplying a number of predetermined sampling rates, a base clock for supplying base clock pulses at a predetermined frequency, means provided with the sampling rate means and with the base clock

-3- are connected in accordance with resp. predetermined sampling rates divide the frequency of the base clock pulses to obtain sampling clock pulses substantially coinciding therewith, and 5 control means to obtain a predetermined number of bay clock pulses for each predetermined sampling rate, "the control means choosing a subsequent sampling rate after all of the predetermined number of sampling clock pulses for the previous sampling rate and prior to the next base clock pulse.

It is also an object of the invention to provide a sampling clock which is suitable for the coherent switching from one sampling rate to another during the acquisition of a waveform.

The invention further contemplates making more useful use of the 15-shape memory space by sampling at rates proportional to expected rates of change of the waveform.

The invention additionally provides a digital time base for a waveform acquisition system in which the sampling rates. and the numbers of samples to be obtained for each sampling rate are programmable.

The invention is elucidated with reference to the drawing: fig. 1 shows a block diagram of a digital time base according to the invention; Fig. 2 shows an example of a compact idealized waveform 25 of an analog signal to be digitized at different speeds; and FIG. 3 shows a time diagram showing the associated speed changeover.

Fig. 1 shows a block diagram of a time base for an acquisition system in which analog signals are fed via an input terminal 10 to a waveform 30 acquisition circuit 12, which circuit may comprise known sample holdings and analog-digital converters as used in known digital oscilloscopes. The acquisition circuit 12 responds to the input waveform in accordance with sampling clock pulses from a base clock 14 and a sampling clock gate 16 in the digital time base 35 circuit. An address counter 18 is incremented by the sampling clock pulses and provides address signals for storing digital representations of the analog samples in a waveform memory 20.

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Although waveform memory systems. Require both acquisition and readout chains, the invention relates only to acquisition; therefore, a description of the readout chains has been omitted. It is hereby assumed that reading for display purposes is within the knowledge of one skilled in the art and can be accomplished using known techniques.

A time base control circuit includes an -fI or N counter 22. dividing the base clock rate by the preset count modulus value from a sampling rate memory 2 ^. The base clock 1V can be a crystal-controlled oscillator that supplies clock pulses with a fixed frequency of, for example, 100 MHz. The -fK counter 22 may include any number of commercially available counters that count down a pre-settable number of clock pulses and provide a final count signal at the end of each countdown period. In this particular embodiment, a synchronous row of 15 counters has been employed to obtain a variable phase counter suitable for dividing the clock signal from one to 10,000 in step -pen of E = A x10. , where 1 <> A £ 10. and 0 £ B <3 and where both A and B are integers. The sampling rate memory 2k may be a random access memory (RAM) operated as a first-in / first-out (FIFO) unit controlled by an address counter 26. The address counter 26 also controls a memory 28 for the numbers of samples and may also be a RAM operated as a FIFO unit. A sample number counter counts clock pulses from the sample clock gate 16. A digital comparator 32 compares the counted output signal of the counter 30 with the contents of the addressed portion of the memory 28 and if there is a match, the comparator provides a signal which is fed via an elevation track to the address counter 26 whereupon it is incremented and selects the next sampling rate or counting modulus or counting modulus in the memory 2¼ and the next number of samples in the memory 28 When the final count value of the counter 30 is reached, such a counter provides a signal which is applied to a reset gate 36 for resetting the system therewith.

The operation of the acquisition system will now be clarified by means of an example. Fig. 2 shows a compact idealized waveform of an analog pulse to be digitized. The waveform shown is in the form of a wide pulse with relatively fast rising and falling edges.

8100806 -5-

It is said that this waveform is fed to the input terminal 10 and that the available memory space of the waveform memory 20 includes 1000 memory locations and that further the clock brightness of the base clock is 100 MHz. The waveform of Figure 2 can be divided into three segments 5 with resp. duration of 2 yus, 20 ms and 600 ^ us. These three segments are bounded by points BP1, BP2, BP3 and BPif. The segment BP1-BP2 must be sampled at a rate of 100 MHz and 200 samples must be sampled. The segment BP2-BP3 must be sampled at a rate of 10 kHz and 200 samples must be taken. Segment 10 BP3-BPit must be sampled at 1 MHz and 600 samples must be sampled. This yields 1000 samples for it. completely filling the memory 20 and also provides complete information about the waveform. BP1 is believed to be the trigger point. The first step is to load the predetermined information about the sampling rates and the numbers of samples for each rate into the time base control systems el.

The system was reset in the beginning. This is done by supplying a logic low signal to an input of reset gate 36, which is a poort gate, from an input terminal 40. The other input, 20 for the terminal 30 count value, receives a logic high signal. The output of the reset gate 36 thereby becomes low, so that a reset is obtained from the address counter 26, the sample count counter 30, the memory address counter 18, and a trigger flip-flop k2. After the reset of the system, for example, with the aid of a pick-up resistor connected to a suitable power source, a logic high signal is fed to the input terminal U0 and thereby to the reset port 36, thereby making its output high. Likewise, a logic high signal is fed from input terminal 1A to the elevation track 3, which is also an EH gate, and a logic high signal 30 is also fed from comparator 32 to the other input of the elevation. 3 ^ so that its output is high.

Subsequently, the data for the sample rate and the number of samples to be taken, for example in the form of predetermined data words, are entered in the resp. memories 2h and 28 are loaded. This is performed by first placing the data for the segment BP1-BP2 on the load lines and applying a load pulse to an input terminal h6. Then, the address counter 26 is incremented by feeding 8100806-6 from one to a logic low level. going pulse at the input terminal luk Then the data for the segment BP2-BP3 is placed on the load lines and the process is repeated until all data regarding the sampling rate and the number of samples to be taken are loaded. After the loading process described above, the system is reset again, so that the address counter 26 returns to its initial position. By resetting the trigger flip-flop k2, the reset pulse blocks the memory address counter 18 and the sample number counter until the system is activated by applying a trigger or trigger pulse to an input terminal. Thus, although the time base operates at the first rate, all samples generated by the waveform are ignored. acquisition chain 12 has been taken prior to impacting the system.

In a manner as used with known oscilloscopes, a trigger signal can be derived from the analog input signal. For example, the analog signal may first be processed by a preamplifier in which a trigger signal is taken, which is then compared to an adjustable voltage level for generating a trigger signal at any desired point of the waveform representing the analog signal. In such a case, the analog signal is fed from the preamplifier to the waveform acquisition chain through a delay line so as to have sufficient time to activate the time base chains and not miss any of the analog signal. The trigger signal is fed through the input terminal ^ -8 to the clock input of the flip-flop k2, thereby increasing its Q output, so that the address counter 18 and the sample number counter 30 'are released. As stated earlier, the time base is already operating at the first speed, namely 100 MHz, since the base clock signal is divided by one. The output for the final count value of the counter 22 is logic low and the sampling clock gate 16 is accordingly an 0F gate; which transmits the descending sampling clock pulses when both inputs thereof are low. The address counter 18 and the sample number counter 30 start counting the sample clock pulses and the resulting samples are stored in addressed memory locations of the waveform memory 20. When the 200th sampling clock pulse 35 has been counted by the counter 30, the output of the comparator 32 goes low, causing the output of the increment gate 3 ^ to go low, so that the address counter 26 is incremented, so that in the memories 2.b and 28 the 8100806 data for the sampling rate and the number of pulses to be taken associated with the time segment BP2-BP3 are selected. The base clock has a clock period of 10 ns at 100 MHz, and the previous comparator switch, the address counter increment and the refresh of the memory output 5 occur in less than 10 ns, so that the I counter 22 is refreshed at the new rate before the next basic clock pulse occurs. Thus, at the breakpoint BP2, the sampling clock pulse output of the sampling clock gate 16 is coherently switched from a speed of 1 MHz to a speed of 10 kHz and no indefinite time windows occur in the stored waveform.

This process is repeated between points BP2 and BP3, with the waveform acquisition chain 12 bringing in another 200 samples and at the breaking point BP3, the sampling clock pulse output of the sampling clock gate 16 is consistently switched from a rate of 10. kHz to a rate of 1 MHz. Another 600 samples are taken in between points BP3 and BPU, which completely fills the memory.

At breakpoint BPit, the sample number counter 30 reaches the final count value, thereby obtaining a low output signal which is fed to the reset port 36 for resetting the system 20 in the manner described above.

In Fig. 3, the related speed switching is depicted in a time diagram. For the sake of clarity and a better understanding of the related speed switching, speeds other than the aforementioned have been chosen. Between points BP1 and BP2, the base clock is divided by one 25 and a sample clock pulse is provided for each base clock pulse. At the point BP2, the rate is shifted and the base clock is divided by five, with the first banana clock pulse occurring simultaneously with the fifth base clock pulse following BP2. As a result, the switching is coherent or coherent in that there are no indefinite or unknown time windows in the output of the sample clock. At the point BP3, the sampling clock rate is again connected coherently and the base clock is divided by two. It should be noted that the sampling clock pulses coincide with the base clock pulses and that the break points occur at the sampling clock pulses.

8100806

Claims (6)

2. Digital time base according to claim 1, characterized in that the means for supplying a number of sampling rates are formed by a first memory, the control means being formed by a second memory for storing the number of sampling clock pulses for each sampling rate, a counter for counting the supplied sampling clock pulses and generating a control signal when the number of counted sampling clock pulses corresponds to the number extracted from the second memory, and an address counter which responds to the control signal for selecting the next sampling rate in the first memory and the next number of sampling clock pulses. the second memory. 3. Digital time base according to claim 1, characterized in that the means for dividing the clock frequency are formed by a counter which counts down clock pulses in accordance with a counting modulus represented by the selected sampling rate to obtain the sampling clock pulses. h. Digital time base according to claim 3, characterized in that the means for dividing the clock frequency are further formed by A gate responsive to the simultaneous occurrence of the counter output signal and the hash clock pulses to obtain the sampling clock pulses. 5. Digital time base with associated rate switching characterized by a base clock for delivering hasis clock pulses at a predetermined frequency, a variable module counter connected to the base clock for dividing the frequency of the base clock in accordance with the resp. 10 moduli of a number of predetermined counting moduli and means for switching the counting moduli such that the switching takes place between a divided base clock pulse and a. next undivided base clock pulse. Digital time base according to claim. 5 characterized by means for storing a number of predetermined counting moduli and a number of predetermined numbers of distributed hasis clock pulses to be supplied. Digital time base according to claim 6, characterized by a counter for counting a number of distributed hasis clock pulses. 8. Digital time base according to claim 7, characterized in that the switching means comprise means for generating a switching pulse when the counted number of distributed hash clock pulses corresponds to one of the predetermined numbers of pulses to be supplied, the means for storing the switching pulses. predetermined counting moduli and predetermined numbers of pulses respond to the switching pulse to obtain a next counting modulus and a next number to be supplied. 8100806