NL2005656C2 - Multilayered electronic carriers such as printed circuit boards or ic's, system comprising a multilayered electronic carrier method for decoupling multilayered carriers and use thereof. - Google Patents

Description

Multilayered electronic carriers such as printed circuit boards or IC's, system comprising a multilayered electronic carrier method for decoupling multilayered carriers and use thereof 5

Field

The present description relates to decoupling of multilayer electronic carriers such as printed circuit boards (PCB) or integrated circuits (ICs). The invention also relates to a 10 PCB assembly (PCA) comprising a PCB and one or more packages. A package can contain one or more active integrated circuits (ICs). The invention further relates to a power distribution network (PDN) decoupling method.

15 Background ICs (Integrated Circuits) are manufactured on semiconductor wafers with several layers of active circuitry. The wafer is cut into separate semiconductor dies which are mounted into packages and electrically coupled to PCBs. The ICs, IC-20 packages and PCBs are all example of electrical structures that can have several layers including a ground plane, and a supply plane and various interconnect planes. The semiconductor dies are connected and sealed inside a package from which pins or balls extend. The pins or balls can 25 extend to a ground plane, supply plane and external circuitry. These pins or balls allow the package to be coupled to a PCB (Printed Circuit Board).

The package containing the semiconductor dies is generally 30 coupled to a PCB and powered by a system power supply located thereon or connected thereto. The system power ,, supply is often connected to a system reference ground (ideally at a voltage potential of 0 Volts). The system 2 power supply is also connected through power and ground leads to the supply and ground planes for operating the semiconductor dies inside their packages.

5 A package containing a semiconductor die that is coupled to the PCB will be referred to as printed circuit board assembly (PCA).

An example PCB is a Eurocard PCB (E-PCB). An E-PCB measures 10 160 x 100 mm, and can have a double-sided copper structure as ground and supply plane. In an embodiment the E-PCB is 1,5 mm thick and comprises the material FR-4 or any other kind of dielectric insulating material. Such a E-PCB will have a transmission line propagation delay of about 1,2 ns 15 in-between the ground and supply planes. Further these ground versus supply plane E-PCB has a characteristic impedance of about 2,5 Ω.

When the insulation thickness in-between the supply and 20 ground planes is further reduced down to 100 pm, the characteristic impedance will lower, reduced to for example 0,17 Ω for the same kind of board shape while the propagation delay remains the same; v = V(p0pr·Bo£r) , where pr generally equals 1 and 4,2 < sr < 4,7 for FR-4.

25

In a multi-layer PCA PDN structure, the characteristic impedance between the ground and supply planes is in the order of a few Ohms or even less. Again for a FR-4 spacing of 1,5 mm, the characteristic impedance will be about 2,5 Ω 30 and for a FR-4 spacing of about 100 pm it will be about 0,17 Ω. Structures down to tens of pm of insulating material are ? commercially available.

3

However, when a transmission line is left open-ended or short-circuited by using multiple ceramic capacitances with very low RF losses, steep resonances result.

5 Since the system power supply is often located a substantial distance away from the active semiconductors, long time delays and high inductance associated with the power and ground leads are introduced into the IC's power distribution network (PDN) system. The PCA's PDN system includes among 10 other things all the connections between the semiconductor die's active components in their packages (e.g., core or I/O drivers) and their power sources (e.g., system power supply). As a result, the packaged components as well as the PCA as a whole operate in a suboptimal manner.

15

At higher clock speeds (for example higher than 1 GHz) and faster clock signal rise times (for example less than 100 psec), the power delivery design of integrated circuit packages, results in too long delays by a high equivalent 20 loop inductance or long delaying transmission lines.

The loop inductance of the power delivery system may be reduced using a decoupling circuit formed by multiple bypass capacitors. Bypass (decoupling) capacitors are also used to 25 reduce electrical noise, to miminize the decoupling current loop area and as such to suppress unwanted radiation. The electrical noise is generated by the continuous switching of the transistors in the IC's circuit and amplified by the resonances caused by capacitive and inductive parasitics in 30 the total on- and off-chip decoupling PDN.

The supply and ground planes of a PCA can also be used to decouple the supplies of ICs. A large amount of decoupling 4 capacitors is populated in parallel to these supply and ground planes forming the total PDN. In an embodiment a decoupling connection, comprising a single or multiple capacitors, couples the ground and supply planes at or near 5 the circumference of the packed semiconductor die.

A further parameter in IC design is the required surface area on the IC/package/PCB. Specifically decoupling elements are preferably absent from the surface area on the PCB/PCA.

10

Most of the PCB/PCA problems with respect to power integrity signal integrity and EMC are the result of resonances caused by the PCB/PCA PDN and the large amount of decoupling capacitors populated in parallel to this PDN structure. When 15 the supply and ground planes of a PCB/PCA are used to decouple the supplies of ICs, the decoupling current will flow all over the board layer area leading to excessive current loop paths which induce ground and supply noise which adds up to critical signals and to unintended RF 20 emission. Furthermore, large PDN loop resonances are also caused through the IC's. Those resonances will substantially add to the ground bounce noise as the IC's internal capacitance is part of that resonant PDN decoupling loop.

25 Also, putting a large number of decoupling capacitors (10 > N > 200) in parallel to the IC supply nodes will Increase the local decoupling capacitance i.e. instantaneous available charge. However, the reduction of total equivalent series resistance and series inductance will only occur 30 proportionally when the noise current from the IC is equally distributed along all circumference pins at equal level and phase. Any excitation offset from the center of the IC die (which is always the case) will lead to phase differences 5 and skew towards the surrounding decoupling capacitors placed, reducing their effectiveness.

It is not beneficial for the application as a whole to get 5 all instantaneous switching noise current from the IC through the IC-package onto the PCB/PCA as the maximum ground bounce will result across the equivalent package inductances and noise will be generated on the PCA rather than being confined into the chip area. This typically 10 results in an increase of the decoupling loop area on-chip versus on-chip to the PCB/PCA by a factor of 10 to 100.

When a transmission line is left open-ended or RF short-circuited by capacitances with very low RF losses, steep 15 resonances result. The frequencies of these resonances are determined by the electrical path length from the point of excitation (IC supply and ground pins) to any RF short-circuiting decoupling capacitance and/or open-end of the PCA. Additionally resonances do occur between the RF short-20 circuiting decoupling capacitance's location and the open-end of the PCA in any direction.

GOAL

It is a goal of the invention to improve a power 25 distribution network on a substrate such as a multilayer carrier. In particular the decoupling of the PDN of multilayer carriers such as an IC, an IC-package, PCB or a PCA, preferably a multi-layer PCB/PCA is to be improved.

30 According to another aspect it is a further object to provide an improved decoupling method for a power distribution network on a substrate such as a PCB/PCA.

6

For some embodiments disclosed herein it is a goal to allow for high supply currents to be distributed over the PDF without causing severe resonances between the supply and ground planes used. For some embodiments disclosed herein it 5 Is also a goal to achieve high signal integrity and good EMC. For some further embodiments disclosed herein it is a further goal to prevent the necessity of application restrictions .

10 SUMMARY OF THE INVENTION

In one aspect, the present invention provides a substrate.

In an embodiment a multi-layered substrate is provided comprising a multi-layer structure, such as a PCB or a package structure or silicon dies of IC's. The substrate 15 (PCB, package structure or silicon die) can have a power distribution network. The substrate comprises at least a supply plane, a ground plane and a decoupling circuitry.

In an embodiment of a PCB the supply and/or ground planes 20 are configured to be electrically connected to a package containing semiconductor circuitry.

In an embodiment the decoupling circuitry comprises at least a (non-ideal) capacitor. In an embodiment the decoupling 25 circuitry further comprises a resistor coupled in series with the capacitor or equivalent series losses embodied in the capacitor. By providing a decoupling circuitry of a resistor and capacitor in series, a decoupling circuitry is provided that will terminate transmission lines represented 30 by the supply and ground planes of the substrate, such as the PCB, while representing sufficient charge buffering to .

sustain operation of the packages connected thereto.

Reflection from the decoupling connection can then be 7 neglectable. The PDM impedance as seen at the IC's supply and ground nodes can remain stable.

The characteristic impedance of the ground and supply plane 5 structure {determined by geometry and material properties) can be determined. In an embodiment the total impedance of the decoupling connection is in the order of the characteristic impedance.

10 By adjusting the decoupling circuitry's capacitance and resistance values to the characteristic impedances of the substrate, such as the PCB, supply and ground planes, reflection can become neglectable.

15 In this application 'in the order of' will be interpreted as 0.1*N*Zq < Z < 10*N*Zo and more specifically 0.5*Z0 ^ Z ^ 2.0*Z0. This decoupling circuitry impedance will allow terminating the transmission lines by their partial characteristic impedance.

20

In an embodiment the decoupling connection is located at a circumference of the substrate, in particular PCB/PCA. This will allow terminating the transmission lines down at the edge of the board or its boundary and optimise for a circuit 25 density in the component's area of the board.

In an embodiment a decoupling circuitry comprises multiple decoupling connections between the supply and ground plane. At least one of the decoupling connections comprises a 30 capacitor and resistor in series coupled to the ground and supply planes.

8

In an embodiment an IC, IC-package or board edge circumference is sub-divided in N equal parts. In such an embodiment each part can comprise a decoupling connection, the decoupling connections together forming the decoupling 5 circuitry. Multiple decoupling connections allow local decoupling.

In an embodiment the impedance of multiple, most or in an embodiment each decoupling connection is in the order of 10 Ν·Ζ0: 0. l*N*Zo < Z < 10*N*Zo or more specifically 0.5*N*Z0 < Z

< 2.0*N*Zo. This decoupling connection approximates a first-order optimum, as the real current distribution at the edge of the substrate or PCB/PCA is considered unknown for real applications. An explanation could be that the generated 15 noise becomes a travelling wave which will be absorbed by the transmission line load impedances represented by the decoupling connections in parallel in each direction of propagation.

20 In an embodiment the load resistance in a decoupling connection, when N decoupling connections are provided, is in the order of R = N-Zq, wherein N may extend to infinite: ». This will allow obtaining a total decoupling impedance of Zq, in each direction of propagation, which is a first order 25 approximation of a optimal decoupling.

In an embodiment the capacitance of a capacitor in a decoupling connection is in the order of some nF. This will assure the necessary DC charge buffering and RF decoupling.

30 The total capacitance required will be determined by the average supply current needed versus time and the maximum supply bounce allowed, in accordance with C-AV = I-t = Q [C] 9

In an embodiment both RF decoupling as well as a low, but constant impedance versus frequency (Q<2) can be achieved by providing a decoupling connection having a impedance, at the ÏC's supply and ground port, in the order of Z0/4 for 5 rectangular PCB substrates. In rectangular PCBs, as seen from the supply and ground contacts of the ICs connected thereto, the decoupling current will propagate into each direction of the PCB equally.

10 In accordance with the invention the decoupling circuitry allows lowering the resonance frequency by adding inductance, which allows a lower series resistance, specifically for high frequencies. This lower resistance is also easier to integrate in the decoupling circuitry. Part 15 of the damping resistance is already provided for as a result of the characteristic impedance of the PDN structure.

The self inductance is primarily the result of path length, lead frame and wiring. The self inductance is further lengthened/enlarged by trace structures on the PCB.

20

In an embodiment the PCB comprises rectangular planes and each decoupling connection of N decoupling connections has a series resistance of about N*Zq. This will eliminate the need for low ESL (inductance} capacitor designs as the RF 25 impedance will be dominated by the equivalent (or external) series resistance (ESR).

In embodiment comprising a rotation symmetric substrate, the decoupling impedance of the decoupling circuitry as seen 30 from possible supply and ground contacts, is in the order of Ζο/2π. It is noted that the impedance in a rotation symmetric * substrate, as seen from supply/ground contacts, in particular supply and ground contacts on a PCB for 10 connecting to a IC, is irrelevant of a certain offset from its center as the decoupling current will propagate as a travelling wave into each direction of the substrate equally.

5 With any (combination) of the above embodiments it is possible to obtain a substrate with a power distribution network wherein an under- or overshoot in excess of 6 dB (factor of 2} compared to the excitation voltage: i-Z0/4, is absent, wherein i = the peak current as drawn instantaneous 10 by the IC connected. Such an under- or overshoot means that the termination impedance at the end of the transmission line may not deviate more than a factor 2 from its nominal value.

15 These and other features and advantages of the invention will be presented in more detail below with reference to the associated drawings.

In an embodiment the printed circuit board carries part of 20 the total power delivery system. In an embodiment the decoupling connection is attached to the power delivery system to stabilize the impedance of the power delivery system over a broad frequency range.

25 In an embodiment the supply and ground planes being positioned as successive substrate layers respectively.

In an embodiment a dielectric insulator material is positioned between the supply and ground planes.

In a further embodiment the substrate comprises a 3-layer PDN topology. In that embodiment the supply plane can be embedded in-between two ground planes which lowers the 30 11 effective RF impedance by 2 (at the cost of just one extra layer).

In an embodiment the supply plane area can be reduced such 5 that a single ground ring can be added to that same (supply) layer which is, by means of vias connected to the ground layers on top and below. The decoupling connections can then be integrated on the supply layer between the outer grounded ring and the inner supply plane either as embedded discrete 10 components or as resistive silk with a capacitive compound in series, similar to N —

In an embodiment a further decoupling circuitry, in an embodiment comprising multiple decoupling connections is 15 electrically connected to a second supply plane and a second ground plane. The second supply and ground planes are located within a multilayer PCB. Vias at the supply and ground positions of a package can provide connections. These vias shall be in parallel at minimum spacing interval to 20 minimize the loop areas involved. Again the decoupling circuitry can be positioned at a circumference of the PCB.

In an embodiment multiple pairs of ground and supply planes may be provided and multiple decoupling connections can be 25 provided between each of these ground and supply plane pairs that may be used in parallel in a PCB/PCA structure.

Multiple, most or in an embodiment each (N) decoupling connection comprises at least a resistor and a capacitor in series.

30

In an embodiment, when ground/supply planes (in multi-layer boards) are in parallel, coupled by through plated vias, each pair of planes belonging to one another is terminated 12 by providing a suitable decoupling connection comprising a series resistor or series resistance.

Supply decoupling currents will flow in-between the 5 ground/supply planes, whereas the functional signals will flow on top of these planes between the signal traces and the ground planes to which these signals are referred. At higher frequencies, noise currents will only propagate in-between the supply and ground layer structures due to 10 proximity (mutual coupling and skin) effects. Though ground planes are single solid conductive structures, the current density distributions at top and bottom become fully insulated from one another at higher frequencies.

15 In an embodiment the required series inductance solely towards the package supply pins, including losses to dampen the resonances towards the ICs being supplied and the system power supply located thereon or connected thereto can be integrated on the PCA as a small spiral, hexagonal or square 20 shape trace structure.

In an embodiment small extra series inductance are provided, increasing the total loop impedance to lower the resonance frequency of the circuit topology as a whole to enable 25 dampening. In a PCB this will provide attenuation between the IC's noise source and the PCB PDN structure.

In order to dampen the resonance of the in-package/ on-IC capacitance and the interconnect wiring towards the PCB PDN 30 supply and ground planes the trace width is adapted to provide the necessary RF losses. At low(er) resonance frequencies to be dampened, less loss resistance will be required, as: 13 Q = r3/ (mre sonancehcotal) ~ ^ (I-'totalqu.lvalent) ' Rs which preferably is less than 2. Ltotai is the sum of 5 inductances of the whole loop,' equivalent is the equivalent capacitance of on- and off-chip/in-package capacitance in parallel and R5 is the total lóss resistance being the sum of Z0/4 plus the losses in the extra inductance structure as the leadframe and bonding wire resistances are being ignored.

10

In an embodiment a decoupling connection is provided comprising a capacitor with integrated resistance. This would allow minimizing the board space further. Due to the required ESR of the decoupling, the parasitic equivalent 15 series inductance (ESL) of the decoupling remains neglectable up to several GHz.

In an embodiment the decoupling circuitry/connection comprises a ceramic or electrolytic decoupling capacitor. In 20 PCB/PCA production processes, even capacitive compound can be used in-between the supply and ground planes i.e. towards the resistive silk to achieve the equivalent capacitance necessary with the decoupling elements to lower the board space component count further.

25

In a prior art decoupling connection a capacitor could be connected to the planes using silver or palladium electrodes. However in any of the embodiments according to the invention cheaper conductive materials can be used to 30 obtain the required equivalent series resistance (ESR) embedded in the capacitance itself. In PCB/PCA production < processes, resistive silk can be used to achieve the necessary equivalent series resistance necessary with the 14 decoupling elements to lower the component count even further.

In an embodiment the substrate PDN, such as the PCB/PCA PDM, 5 is terminated by a decoupling circuitry having N decoupling connections along the circumference of the board. In an embodiment the connections connect the successive and adjacent supply and ground plane structures. Parameters for the arrangement of the decoupling connections are derived 10 from the thickness of the insulation material between the supply/ground layers and the PCA board material used. In an embodiment the separation (s), i.e. between N individual decoupling connections along the substrate circumference (Lc) is determined by the minimum critical wavelength, wherein 15 λ™.,,, to be satisfied; s ^ λπύ.η/2. The number of connections is given by N = Lc/s.

In an embodiment N is in the order of Lc/s, that is: 0.1 *

Lc/s < N < 4 * Lc/s 20

In the embodiment of a E-PCB, the circumference is 0,52 m.

When the maximum frequency of interest to be decoupled is 10 GHz, λ = 0,03m/V8t, wherein if FR4 is used, sr(FR4} = 4,7, resulting in a λ^η = 13,8 mm. s i Xmin/2 7 mm.

25 N becomes 0,52/7-10-3 * 75 decoupling devices along the total E-PCB circumference.

In an embodiment corresponding to N e.g. in the embodiment comprising the resistive silk and capacitive 30 compound all along the circumference of the PCB, the maximum frequency of application is no longer restricted. « 15

In yet another aspect, the present invention provides a method of forming a substrate having a power distribution network, such as a PCB, a package structure or a silicon die. The method comprises providing a substrate, the 5 substrate having a supply plane and a ground plane. In accordance with an embodiment a decoupling connection is provided between the supply plane and the ground plane, the decoupling connection comprising a resistor and a capacitor in series.

10

In an embodiment the method further comprises determining the characteristic impedance of a supply plane and ground plane and providing the decoupling connection with impedance in the order of the characteristic impedance.

15

In an embodiment N decoupling connection are provided. In an embodiment the decoupling circuitry or decoupling connections are formed inside the substrate as interconnections and form an integral part of the substrate. 20 In another embodiment the decoupling circuitry is positioned at or near the circumference of the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will be understood more 25 fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention. The drawings, however, should not be taken to be limiting, but are for explanation and understanding only.

30 FIG. 1 is a schematic view in perspective of a substrate, here a PCA, with a decoupling circuitry comprising decoupling connections according to an embodiment of the invention; 16 FIGs. 2a and 2b are cross-sectional side views of embodiments of a PCB showing ground and supply planes with embodiments of a decoupling connection according to embodiments of the invention; 5 FIG. 3a-c are impedance graphs of resonance properties as a function of frequency measured for an E-PCB having an open decoupling, a short-circuited decoupling and a decoupling connection according to the invention; FIG. 4 shows an embodiment of a process to manufacture a PCB 10 according to an embodiment of the invention; FIG, 5 is a schematic circuit diagram of PDF design according to an embodiment of the invention; FIG. 6 is an embodiment of a total PDN design according to the invention.

15

DETAILED DESCRIPTION

Reference will now be made in detail to specific embodiments of the invention. Examples of the specific embodiments are illustrated in the accompanying drawings. While the 20 invention will be described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the invention to such specific embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be 25 included within the spirit and scope of the invention as defined by the appended claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without 30 some or all of these specific details.

17

In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention, 5 In order for a package to operate, a power source having power (or positive) and ground (or negative) connections is generally required. A power source is required to operate the core and I/O drivers within the package. However, depending on the location of the power source, a different 10 amount of time delay and SSN will occur between the core and the I/O drivers and the power source.

One approach involves attaching decoupling capacitors as close as possible around the package on the PCB. However, 15 this approach uses a large amount of board space and produces a relatively high decoupling current to flow between the package and the PDN on the PCB down to the capacitor locations. Furthermore, resonances occur between the package, the local decoupling capacitors, the power 20 source (i.e., its decoupling capacitors), the PCA in-between and up to the edges of the PCA.

Every structure of supply and ground planes of a PCB, in particular an E-PCB has a characteristic impedance, Zo.

25

Figure 5 is a schematic circuit representation of a E-PCB. The terminated PCB structure/decoupling circuitry is represented by a resistance R7 and capacitor C7. As the E-PCB has a characteristic impedance of about 2,5 Ω; with an 30 FR-4 layer being 1,5 mm thick, R7 = 2,5/4 = 0,625 Ω.

Typical path length delay in FR-4 is 7 ps/mm, to be used with the physical path length/distance in-between the 18 decoupling capacitors. An example value for the delay of transmission line propagation can be 1,2 ns.

Figure 5 shows multiple caps in parallel with a DC supply 5 source at a larger distance. Transmissionlines are terminated by C7 in series with R7. Values for L5-L7 can vary in the nH domain, e.g. 1-10 nH. Capacitors C4-C6 can have values in the order of nF, e.g. 1-1000 nF. R4-R6 can have values in the order of 10-100 mQ. The L8 can have a 10 higher impedance, e.g. in the order of 10-100 nH.

Cl and R7 form together a representation of a decoupling circuitry, here represented as a simple connection comprising a resistor and capacitor in series. C7 and R7 15 allow transmission lines to be terminated.

In any of the embodiments, one, two or more (N) decoupling connections 23 are coupled to an edge or side of a PCB/PCA. The decoupling connections 23 and 23b are shown 20 schematically and can comprise several (connected) elements.

If the supply and ground planes extend to the edges of the PCB, then the one or more decoupling connections may be connected directly to the ground and supply planes of the 25 PCB. This eliminates any loop inductance. Alternatively, the decoupling connections may be connected using vias.

The decoupling connections together form the decoupling circuitry. The circuitry according to the invention 30 comprises at least one decoupling connection having a capacitor and a resistor.

19

In an embodiment wherein a PCB 15 includes multiple substrate layers with several ground planes and supply planes formed on them, that PCB 15 can also include at least one decoupling connection. The decoupling connections can be 5 coupled to a side/edge of the supply and ground planes. In general, decoupling connection is electrically connected to the supply and ground planes.

Ground and supply planes of a multi-layer PCB are typically 10 associated with an IC's power delivery system. As such, the ground and supply planes should carry different voltage potentials. For instance, ground planes may have a negative (-) or zero potential whereas supply planes may have a positive (+} potential.

15

In an embodiment the ground and supply planes are made of a conductive material (e.g., Cu) and normally grouped together in pairs. According to a specific embodiment, an insulating dielectric material is formed between each pair of planes, 20 thereby allowing the pair to act as a small decoupling capacitor.

FIG. 1 is a diagram of a portion of a PCA 11 in perspective view. The PCA 11 has an IC, chip or die 13 attached to a PCB 25 15. The package/PCA may also include a cover or integrated heat spreader (not shown) attached and sealed to the PCB to cover and protect the package. Where suited, the integrated heat spreader should encapsulate the active die having independent contact pins/balls at all four corners to the 30 top layer 14 of the PCB.

20

Once a suitable IC is chosen, the IC can be attached to a corresponding PCB 15. PCB 15 may have any suitable set of dimensions and can be a Eurocard-PCB.

5 The package may be any of a variety of different types g including a microprocessor, microcontroller, ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), DSP (Digital Signal Processor), memory, memory controller hub (MCH), I/O (Input/Output) 10 controller hub (ICH), graphics controller, etc.

The PCB may be formed from any rigid dielectric substrate, such as a standard PC (printed circuit) board material, for example, FR-4 epoxy-glass, polyimide-glass, 15 benzocyclobutene, Teflon, other epoxy resins, injection molded plastic or the like or ceramic. However, when the ground/supply plane structure of the solid PCA is extended over a flexible part, then the circumference of this flexible part shall also be taken into account with the 20 decoupling connections.

In an embodiment the substrate is about 1.0 mm thick although it may be thicker or thinner, in other embodiments.

25 The package has data, control, and power interconnect (not shown) to the chip. The package and PCB have a package side 14, to which the package is attached and a land side on the opposite side of the PCB (not shown).

30 Between the package side 14 and the land (under) side 10 is an edge 16 around the periphery of the substrate, here PCB. While the package side of the PCB will be partially or completely covered by the package cover, the land side and 21 the edge of the PCB remain exposed. As schematically shown in FIG. 1, decoupling connections 23 are provided along this edge.

5 In the shown embodiment the decoupling circuitry on side 18 comprises Q decoupling connections and side 12 comprises P decoupling connections. In total this rectangular embodiment comprises N (= 2P + 2Q) decoupling connections.

10 As shown in FIG. 1, each edge of the substrate may carry several capacitors. FIG. 1 shows eight capacitors along a PCB edge 18. The appropriate number of capacitors will depend on the size of the PCB, the number of edges to be used, the desired decoupling capacitance and the frequency 15 range to which the decoupling has to apply.

Mounting decoupling capacitors along the PCB edge side surfaces avoids space limitation and trace routing constraints that conventional techniques currently bear when 20 using the top or ground planes of the PCB. Mounting decoupling capacitors along PCB package's side surfaces also can make use of a plated contact pad that directly connects to supply and ground planes or associated traces. As compared to conventional techniques of using vias that can 25 introduce a relatively large ESL value, contact pads have larger contact areas that are used to connect to the supply and ground planes, thereby minimizing the (less critical) ESL value. As a result, decoupling performance can be substantially improved over its suitable frequency range.

In any embodiment a board edge circumference 12, 18 can be sub-divided in N equal parts 9. Each part 9 can comprise a decoupling connection according to the invention.

30 22

In the embodiment according to Figure 1 the resistance of the decoupling connection 23 is in the order of Ν·Ζ0. This RF impedance for the decoupling connection approximates a 5 first-order optimum, as the real current distribution is considered unknown for all operation modes of the PCA.

In Figure 1 a further embodiment that can be combined with any of the PCBs described herein, having a decoupling 10 connection 23b. The decoupling connection is provided in a cavity 23a created on the circumference of the PCB. All decoupling connections could be received in such cavities.

The cavities are arranged to allow receiving the decoupling connection and allow fixing of the decoupling connection to 15 an edge of the cavity. The cavity forms an at least partially protecting surrounding for the decoupling connections .

The decoupling connection can comprise, in any of the 20 embodiments, a resistor 25 and a capacitor 28.

In the shown embodiment having N decoupling connections, the resistance of a single decoupling connection is in the order of R = N'Zq This will allow obtaining a total decoupling 25 impedance of Z0/4 for the decoupling circuitry, which is a first order approximation of a optimal decoupling for a rectangular PCB. In the shown embodiment the capacitance of a capacitor in a decoupling connection is in the order of x nF. This will assure DC charge buffering and decoupling.

Decoupling capacitor 28 may be constructed in a variety of : ways. Typically, the decoupling capacitor includes a pair of plates separated by a dielectric material. Each plate has a 30 23 different voltage potential applied to it; thereby, allowing the decoupling capacitor to store energy by charging itself or distribute energy by discharging itself. Depending on the application needs, the amount of capacitance (typically on 5 the order of MicrosFarads) can be selected by using different materials and having different square areas for the plates and dielectric. Typically, the plates are made from a conductive material. Preferably, the conductive material has high electrical conductivity characteristics.

10 Examples of conductive materials include Cu, Al, Pt, Au, etc. On the other hand, the dielectric material includes a material with a dielectric constant in the range between 10 and 1000. The dielectric material may include Si02, Si3N4, Nb205, A1203, Ti02, etc.

15

Any of a variety of different capacitors and capacitor types may be used. In one embodiment, the capacitors have a high grade ceramic body with metal electrodes at each end connected by a resistive paste. The end electrodes may be 20 covered in tin or any other lead-less tin alloy to aid in soldering the capacitors to the tabs. The capacitors are designed with the appropriate characteristics required for the particular IC.

25 In various embodiments, the capacitors may be ceramic capacitors, aluminium oxide capacitors, organic capacitors or capacitors made with many other technologies. The capacitors may have from two to many external terminals distributed on two, three or four sides. In addition, the 30 actual and relative dimensions of the packages, integrated circuits, and discrete capacitors may vary widely, depending on design and manufacturing constraints or other factors.

24

For carrying power to the IC, the substrate has ground 17 and supply 19 planes as shown in FIGs. 2a and 2b.

FIG. 2a shows schematically an embodiment of a PCB 15 in a 5 partial side cross-sectional view. The ground and supply planes are shown as parallel and coextensive in FIG. 2a, however, they may be designed in different configurations to suit a particular application, e.g. in the arrangement according to Fig. 2b in which the same reference numerals 10 refer to likewise elements.

With some PCB production processes passive components; capacitors or capacitance, may be integrated in-between the PCB layers in the pre-preg layer. This, in combination with 15 a resistive silk print can eliminate the need for discrete external components at the edge of the PCB.

The ground 17 and supply 19 planes may be made of any conductive material, including copper, aluminium, tin, lead, 20 nickel, gold, palladium, and carbon or other materials and may be insulated on either side by dielectric layers made, for example, of the PCB or ceramic materials mentioned above. In any of the embodiments the ground and supply planes both can have a tab 21, 22 that extends to a common 25 edge of the substrate.

The decoupling connections 23 can be attached to the tabs 21,22 to couple the ground and supply planes. In any of the embodiments the decoupling connection 23 can have two or 30 even three electrodes 29,31 one for each plate. One or two electrodes 29 are coupled to the ground plane 17 Top and , bottom and the other electrode 31 is coupled to the supply plane 19.

25

It will also be appreciated by those skilled in the art that other configurations can be used for electrically connecting the capacitor to the supply and ground planes. For example, 5 capacitor/resistor can be connected directly to the supply and ground planes without the contact tabs 21 and 22.

In an embodiment a glue dot can be provided and is applied to the PCB edge. The decoupling connections 23 can be 10 attached to the PCB edge using the glue and then solder reflow is used to solder the electrodes 29, 31 to the tabs 21, 22.

The decoupling connection 23 comprises a capacitor 28 and a 15 resistor 25. In Figure 2a these two electrical components are shown as separate elements, connected by electrical wiring. However it will be clear that a single electrical component can be provided having the combined impedance of the resistor and capacitor.

20

The resistor 25 and capacitor 28 are connected in series.

The resistor can be connected to the ground plane, but in another embodiment the resistor is connected to the supply plane.

25

By careful selection, capacitors can be found which already have the needed ESR embedded by their production process, topology and materials chosen. In this case the decoupling connection; capacitance with resistance in series can be 30 replaced by a single component.

In another, not shown, embodiment, single layer copper filled vias may be placed on the edge of the PCB and during 26 de-panel, the vias may be cut in half. One side of the via may then be coupled to the ground plane and the other side of the via may be coupled to the supply plane. The decoupling capacitors may be placed across the bisected 5 vias.

Figure 2b shows an example of a multilayer substrate having through vias 30. With the triple plane concept, having ground layers 17 on the outside (top/bottom), and a supply 10 layer 19 in the middle, the impedance is halved. As the decoupling currents run on the inside of the planes, the decoupling needs to be applied accordingly.

In this embodiment, but possibly in any of the embodiments, 15 a grounded guard is added at the edge of the centered layer, which allows confining the whole decoupling structure.

To terminate the supply plane towards the ground planes, in this embodiment, but possibly in any of the embodiments, the 20 decoupling connections are applied between the guard layer (here formed as a ring) and the inner supply layer using decoupling circuitry/connections 23 which consist of a capacitance 28 and a resistive component 25.

25 As the total PDN impedance between the planes is halved, the decoupling connection resistances need to be halved accordingly. This arrangement will also allow (as a result of the halved impedance) reducing the number of decoupling connections in the decoupling circuitry.

Now a calculation example is presented.

30 27

With a 20 nF on-chip capacitance and a total supply and ground path inductance of 10 nH (~ 10 mm of total path length in an E-PCB), the required series/parallel resistance needed becomes 0,703 Ω of which 0,625 Ω is already present 5 by the Z0 of the supply plane example given.

The IC's PDN resonance frequency is only 11,2 MHz while assuming an ideal off-chip decoupling. Thus the dampening resistance with the inductance to be added has to be 78 mQ.

10

An off-package inductance of 4 nH is assumed by PCA trace lengths of 4 mm in total. By using copper with 37 pm thickness on a PCA, the inductance trace width has to be: 15 w-±L— = —i---- = 144,5) pm]

R-T 78-1Ö”3 -37-10"6 1 J

Due to the single off-chip decoupling capacitance, all charge required by the IC will be acquired locally. The ground pins of the off-chip decoupling and the IC's Vss pins 20 shall be star-point grounded at the IC's ground pin locations rather than at the supply pins (this to minimize ground bounce and take the bounce at the supply side).

When the IC is provided with multiple supply and ground pins 25 and the on-chip or in-package capacitance is insufficient to sustain operation, then an off-chip capacitance (electrolytic with some ESR) shall be added in-between those separate supply and ground pins and kept isolated from the common supply and ground plane structure. Doing so, allows 30 for orthogonal paths for the supply versus the decoupling currents. As the supply current with be an average current 28 (all instantaneous charge will be provided through the orthogonal path) the L*di/dt will become minimal.

As such, signal integrity issues due to ground bounce are 5 much improved and all off-chip decoupling currents are confined and kept dampened and separated from the global low impedance PDN structure.

Crosstalk from IC to IC can now pass by the parallel 10 decoupling capacitor through the dampened series inductance to the low characteristic impedance between the supply/ ground planes towards the next series inductance and local parallel capacitance to the next IC.

15 Although the description of the various embodiments refers primarily to using discrete capacitors in conjunction with an integrated circuit package, the various embodiments may also be used with other types of packages, interposers, PC boards or other electronic circuit housings. The various 20 embodiments may be used with various types of electronic assemblies, and are not to be limited to use with integrated circuit packages .

In addition, the various embodiments may be used with a 25 number of different types of packages and packaging technologies, for example, organic or ceramic packages, and technologies such as land grid array (e.g., organic LGA), pin grid array (e.g., plastic PGA or flip chip PGA), ball grid array (e.g., [mu]BGA, tape BGA, plastic BGA, flip chip 30 BGA or flip chip tape BGA), and beam lead.

Instead of, or in additional to, the side or edge mounted decoupling connections as described in conjunction with 29 figures 1 and 2 herein, other decoupling connections may also be use. Such other decoupling connections include package side, land side and embedded chip decoupling.

5 FIG. 4 shows an example of a process for attaching the decoupling connections to the PCB.

At block 41, a group of insulating and conductive substrates are stacked vertically in a fixture. Edges of the substrates 10 are exposed.

The ground/supply plane can be directly accessible by leaving it exposed on the side surface of the substrate layer. Alternatively, it can be indirectly accessible via 15 interconnects, traces, or terminals connected to the supply plane.

Any conventional technique may be used to form the supply and ground planes. For example, etching and deposition 20 techniques may be used. According to one embodiment, depositing a metal layer over the substrate layer is performed to form either the supply plane or the ground plane. Further, the side surface may be located on a periphery of the PCB and/or within a cavity of the PCB.

25

At block 43, the planes (preferably the edges/circumference thereof) that are to be connected by decoupling connections are paste printed with solder. This solder will be used to attach the decoupling connection. At block 45, for example 30 dots of glue are placed on the edge of the substrate in the center of the footprint for each decoupling connection that will be attached.

30

At block 47, the decoupling connection comprising the resistor and capacitor, are attached to the substrate edges using e.g. the glue dots. The decoupling connections may be attached using a tape reel that carries the decoupling 5 connection and an appropriate tape reel dispenser.

Specifically at block 49, the paste printed solder is reflowed to electrically couple the decoupling connection electrodes to the planes.

10

This attachment process may be repeated, at block 51, for any of the other edges or all of the edges may be handled in one process.

15 Other embodiments of the method comprise using contact pads to electrically connect the supply and ground planes to the capacitor. It will be appreciated by those skilled in the art that any technique can be used to electrically connect the supply and ground planes to the decoupling connection 20 (capacitor/resistor}. For example, each contact pad is exclusively connected to either the supply plane or the ground plane, thereby avoiding a short circuit in parallel to the decoupling capacitor's circuit.

25 After attachment of the edge decoupling connections, the rest of the package may be assembled, at block 53, as appropriate for the intended application.

The PCBs described in the present invention may be 30 constructed using any number of methods.

It will be appreciated by persons of ordinary skill in the art that some of the process operations may be substituted, 31 rearranged, omitted, merged, or repeated. For example, repeating operation 51 in coupling another decoupling connection to the supply and ground planes may be performed.

5 Hence, multiple decoupling connections can be implemented on the PCB. Multiple capacitors are advantageous in efficiently providing more capacitance. This is because of the possible longer time constant for delivering energy as required by the active packages.

10

With all of the new. processors in de sub-micron design space, microcontrollers, DSPs, Field probe gate arrays (FPGAs) on-chip and in-package decoupling capacitance is already present to sustain functional operation from cycle-15 to-cycle or even state-to-state.

Figure 6 shows an example of an IC-die 65 in an IC-package 66 with integrated on-chip decoupling 67.

20 Local off-chip decoupling 73 is beneficial to buffer charge when instantly needed.

A schematic view of a PDN PCA 74 is shown. The PCB comprises two ground planes 75,77 and two supply planes 72,76. Nodes 25 connect the planes with the IC-die 65 and other dies.

Further nodes connect the supply/ground planes 72-77 with a power supply 70.

Further away, the DC supply sources, voltage regulating 30 modules (VRM) or low drop-out regulators (LDO), generally indicated with reference numeral 70, will provide the longterm current as required by the IC(s).

32

As a functional requirement, the PCA PDN impedance is preferably low at low frequencies e.g. 1 mO or even less up to 1 MHz (which is the typical output impedance 70 of an active supply regulator (VRM or LDO). This will allow the 5 PCA PDN to handle the average supply currents which can go up to several hundred Amps.

In an embodiment the total PDN impedance could become higher e.g 10 - 100 mQ and even become resistive (lossy) at the 10 higher frequencies. As such, the DC current can flow as intended through the PDN to the DC supply and the higher frequency on-chip currents remain confined to an on-chip area.

15 The ground/supply planes 72-77 need to be connected to an overall DC supply source, VRM or LDO, 70 through a RF series impedance 82 having a damping resistance 83 embedded.

As such this DC supply connection 70 will not inversely 20 affect the low characteristic impedance(s) achieved in-between the supply and ground planes 72-77. The series impedance will be resonance free (RF) and will provide a low impedance i.e. short-circuit 83 at DC only.

25 The ground and supply plane 72,77 form a combination 79. The ground and supply plane 75,76 has a characteristic impedance of Zo in each direction of propagation.

When the supply and ground planes are powered through a 10 -30 100 nH inductance 83, this will be considered as a high impedance above 1-10 MHz compared to PCA's Z0/4.

33

This corner frequency; fc is determined by the largest PDN delay on the PCA: fc = 1/(tpa-max· 1 ·

At the IC 65 load side, a small inductance 84 in the order 5 of 10 -3 100 nH can be applied too towards the single off-chip decoupling capacitance 73, typically an electrolytic capacitbr, near to the IC to be supplied.

In an embodiment, to dampen these two LC-resonant circuits 10 84,72, the on-chip decoupling capacitor 67 and its series package inductance 84 towards the off-chip decoupling capacitance 73 can be used. Further the off-chip capacitance 73 and the small series inductance 85 with a small series/parallel resistance 86 towards the ground/supply 15 planes 77,72 can be used. By this small series inductance, the IC load will not affect the overall PCA PDN characteristic impedance again. When the on-chip or inpackage decoupling capacitance is high enough, the off-chip decoupling capacitor 73 can be omitted.

20

In an embodiment the IC 65 is provided with multiple supply and ground pins (not shown} and the on-chip or in-package capacitance 67 is insufficient to sustain operation. In such an embodiment off-chip capacitance (electrolytic with some 25 ESR) 73 can be added in-between those separate supply and ground pins and kept isolated from the common supply and ground plane structure. Doing so, allows for orthogonal paths for the supply versus the decoupling currents. As the supply current with be an average current (all instantaneous 30 charge will be provided through the orthogonal path) the L»di/dt will become minimal. s 34

As such, signal integrity issues due to ground bounce are minimized and close to all off-chip decoupling currents are confined and kept dampened and separated from the global low impedance PDN structure.

5

Supply plane 76 and ground plane 75 are decoupled using a decoupling connection 90 comprising electrodes connecting the connection 90 to the planes, a resistor 91 and a capacitor 78, The capacitor's capacitance is arranged such 10 as to be suitable for the die 65 or dies that is to be arranged on the PCB. The resistor 91 can be one of N resistors of M decoupling connections between the ground/supply plane. On the other side (left hand side) a further decoupling connection is shown.

15

In accordance to an embodiment of the invention the load resistance in each single decoupling connection is about N*Z0.

20 Figures 3a-3c show typical impedance graphs of resonance properties at a power port on an E-PCB (100x160 mm x 1.5 mm). In the three graphs, the absolute real, absolute imaginary and absolute total impedance are depicted as function of frequency.

25

The impedance is depicted as seen at a supply part on an example RF open ended E-PCB.

FIG 3a shows the Zn parameter as seen at a supply node on 30 the E-PCB, when a PCB having no decoupling connection at all, is used as a function of frequency. Sharp impedance % changes occur. Due to the lack of charge buffering, this is not a practical application.

35 FIG 3b shows the Zu parameter as seen at a supply node on the E-PCB, when a PCB having a decoupling circuitry containing only capacitors are used as a function of 5 frequency. Sharp impedance changes occur at higher frequencies above 400 MHz.

FIG 3c shows the Zu parameter as seen at a supply node on the E-PCB when a PCB having decoupling connection comprising 10 at least a capacitor and resistor in series, is used as a function of frequency. Specifically the E-PCB comprises 26 decoupling connections.

The pattern is far more dampened and therefore improved.

15 Note that the low-frequency impedance is 0,625 Ω, as calculated for the E-PCB. Important to note too is the continuous absorptive impedance (re(Zll)) which achieves dampening most resonances.

20 Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims.

Therefore, the present embodiments are to be considered as 25 illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims .

30 It is to be appreciated that a lesser or more complex semiconductor device, integrated circuit, package or capacitor than the examples described above may be preferred for certain implementations. Therefore, the configurations 36 may vary from implementation to implementation depending upon numerous factors, such as price constraints, performance requirements, technological improvements, or other circumstances. Embodiments of the invention may also 5 be applied to other types of systems that use different devices than those shown in the Figures.

In the description above, numerous specific details are set forth. However, it is understood that embodiments of the 10 invention may be practiced without these specific details. For example, well-known equivalent materials may be substituted in place of those described herein, and similarly, well-known equivalent techniques may be substituted in place of the particular processing techniques 15 disclosed. In other instances, well-known circuits, structures and techniques have not been shown in detail to avoid obscuring the understanding of this description.

While the embodiments of the invention have been described in terms of several embodiments, those skilled in the art 20 will recognize that the invention is not limited to the embodiments described, but may be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.

25 37

Clauses 1. A multilayer substrate, such as a printed circuit board configured to receive an IC- package, a package structure or 5 a silicon die, comprising a power distribution network and further comprising at least a supply plane and a ground plane, and a decoupling circuitry for decoupling the ground and supply plane, the decoupling circuitry being electrically connected to the supply plane and the ground 10 plane, the decoupling circuitry comprising at least a capacitor, wherein the decoupling circuitry further comprises a resistor in series with the capacitor.

2. A substrate according to claim 1, wherein the supply 15 plane and the ground plane have a characteristic impedance (Z0) and wherein the decoupling circuitry has a impedance of at least 10% and e.g. at most 1000 % of that characteristic impedance and more specifically 0,5-2 times the nominal value of the characteristic impedance.

20 3. A substrate according to claim 1 or 2, wherein the decoupling circuitry comprises one, two or multiple (N) decoupling connections, each comprising at least a capacitor and resistor in series, between the supply plane and ground 25 plane.

4. A substrate according to claim 3, wherein the multiple (N) decoupling connections are generally equally spaced, surrounding the area to be decoupled.

30 5. A substrate according to claim 3, wherein the area to be , decoupled has a characteristic impedance (Z0) and wherein the 38 multiple (N) decoupling connections have a load resistance R, wherein 0,1*N*Z0 < R < 10*N*Z0.

6. A substrate according to any of the previous claims, 5 wherein a supply plane/ground plane has a circumference and the decoupling connection is positioned at or near the circumference.

7. A substrate according to any of the previous claims, 10 wherein a multi-layer substrate, such as a multi-layer PCB, comprises a plurality of substrate layers, the supply and ground planes being positioned successive layers respectively.

15 8. A substrate according to claim 7, wherein a further decoupling circuitry is electrically connected to a second supply plane and a second ground plane that are located within the multilayer substrate.

20 9. A substrate according to any of the previous claims, wherein the substrate comprises interconnect layers. 1 A printed circuit board assembly, comprising: a printed circuit board having a power distribution network, 25 wherein the printed circuit board includes, a supply plane, a ground plane and a decoupling circuitry comprising a capacitor electrically connected to the supply plane and the ground plane; and a package being positioned on the supply plane and 30 electrically connected to the printed circuit board, wherein the decoupling circuitry further comprises a resistor in 5 series with the capacitor.

...........................''".---.'."a 39 11. The assembly of claim 10, further comprising a cover fastened to the package side of the printed circuit to protect the package.

5 :12. The assembly of claim 10, further comprising a package containing the silicon die/IC to protect the IC.

13. The assembly of claim 10, further comprising a silicon die containing the core and I/o drivers to protect the 10 silicon circuits.

14. Method of forming a substrate having a power distribution network, comprising: - providing a substrate having a power distribution network, 15 a supply plane and a ground plane, - forming a decoupling circuitry between the supply and ground plane, wherein the decoupling circuitry comprises a resistance and a capacitance in series.

Claims (12)

A multi-layered substrate such as a printed circuit board arranged for applying an integrated circuit, a package structure or a silicone package, comprising a power distribution network and further comprising at least one power supply surface and a ground surface, and a disconnection circuit for disconnection of the power supply surface and the ground plane, wherein the decoupling circuit is electrically coupled to the power supply plane and the ground plane, the decoupling circuit comprising at least one capacitor, the decoupling circuit further comprising a resistor connected in series with the capacitor. 15 A substrate according to claim 1, wherein the supply plane and the base have a characteristic impedance (Z0}, and wherein the decoupling circuit has an impedance that is at least 10% of and for example at most 1000% of that characteristic impedance and more in in particular 0.5-2 times the nominal value of the characteristic impedance. 3. A substrate according to claim 1 or 2, wherein the decoupling circuit comprises one, two or more (N) decoupling connections, each comprising at least one capacitor and a resistor in series, between the power supply surface and the base surface. A substrate according to claim 3, wherein the plurality of (N) disconnect connections are arranged substantially at equal mutual distances from each other, and surround the surface to be disconnected. A substrate according to claim 3, wherein the surface to be decoupled has a characteristic impedance (Z0) and wherein the plurality of (N) decoupling connections have a resistance R, where Q, 1 * M * Z0 <R <10 * N * applies Z0. 6. A substrate according to any one of the preceding claims, wherein a feed surface / base surface has a circumference and the disconnection connection is positioned at or near the circumference. 7. A substrate according to any one of the preceding claims, wherein a multi-layer substrate, such as a multi-layer printed circuit board (PCB), has a plurality of substrate layers, the feed surfaces and the base surfaces being positioned as respective successive layers. 8. A substrate according to claim 7, wherein a further decoupling circuit is electrically coupled to a second supply surface and a second base surface which are included in the multi-layer substrate. 1 A substrate according to any one of the preceding claims, wherein the substrate has interconnection layers. 2 A printed circuit board assembly comprising: a printed circuit board with a power distribution network, wherein the printed circuit board comprises a power supply surface, a ground surface and a disconnection circuit, wherein the disconnection circuit comprises a capacitor electrically coupled to the power supply surface and the base surface of the printed circuit board; and a packet placed on the power supply plane and electrically connected to the printed circuit board, the disconnection circuit further comprising a resistor in series with the capacitor. 11. Assembly as claimed in claim 10, further comprising an envelope arranged on the package side of the printed circuit board for protecting the package. The assembly of claim 10, further comprising a package containing a silicone / IC for protecting the IC. The assembly of claim 10, further comprising a silicone that incorporates a core and I / O drivers for protecting the silicone circuitry. 15 14. Method for forming a substrate provided with a power distribution network, comprising: - providing a substrate with a power distribution network, a power supply surface and a base surface, 20. forming a disconnection circuit between the power supply surface and the base surface, wherein the disconnection circuit comprises a resistor and a capacitor in series.