CN100539112C - Optimization is to electric power transfer high-speed, the high pin counting apparatus - Google Patents

Abstract

The present invention discloses a high-speed semiconductor device comprising: a substrate having an upper substrate surface, a lower substrate surface, and a perimeter defining the upper and lower substrate surfaces, the substrate The bottom further has an upper substrate ground trace providing an electrical path to the lower substrate surface via a substrate ground via; a solder attached to the lower substrate surface A ball array, the solder ball array includes a plurality of ground solder balls disposed at the perimeter and electrically connected to the substrate ground vias.

Description

Optimizing Power Delivery to High-Speed, High-Pin-Count Devices

This application claims the benefit of US Provisional Patent Application Serial No. 60/547,756, filed February 24,2004.

technical field

The present application relates generally to high speed integrated circuit devices, and more particularly, to a method and system for optimizing to high speed, high pin count semiconductor devices.

Background technique

In recent years, wireless communication systems have increased in number and complexity. This complexity has forced wireless communication systems, especially handheld wireless devices, to utilize multilayer substrates with increased component packing density. The use of multilayer substrates enables segmented power and ground planes to be placed on internal substrate layers. Such configurations can result in long path lengths, for example, between a high speed device and a corresponding decoupling capacitor. Therefore, electromagnetic interference (EMI) issues may arise when using high speed devices on multilayer substrates with power and ground planes designed into multiple segmented regions.

High-speed devices such as microprocessors can operate using very short bursts of current. At high operating speeds, signal propagation delays between bond wires due to mutual and self-inductance, transition noise, and crosstalk degrade the signal. The mutual inductance may result, for example, from the interaction between magnetic fields generated by signal currents in the bond wires between chips and traces on the substrate, and the self-inductance may result from antiparallel currents The interaction of opposing magnetic fields. As the number of inputs and outputs to the chip continues to increase, external connections become more numerous and more complex, and in some cases, result in undesired lengths of bond wire leads and conductive substrate traces . Thus, faster and increasing signal frequencies have created undesired signal propagation effects due to the inductance of package leads or traces.

It can be seen that there is a need for a semiconductor package that can be configured to accommodate and substantially overcome inductance-related defects, EMI issues, and grounding issues so that advantageous aspects of the packaging concept can be implemented in a relatively simple and cost-effective manner. All advantages.

Contents of the invention

In one embodiment, a semiconductor device includes a substrate having an upper substrate surface, a lower substrate surface, and a perimeter defining the upper and lower substrate surfaces, the upper substrate surface further having at least one upper substrate ground trace to provide an electrical path to at least one lower substrate ground trace on the lower substrate surface via at least one substrate ground via; an array of solder balls attached to the The lower substrate surface, and includes a plurality of ground solder balls disposed at the perimeter and electrically connected to at least one substrate ground via.

In another embodiment, a high speed semiconductor device includes: a substrate having an upper substrate surface, a lower substrate surface, an electrical connection to the lower substrate surface via a substrate ground via. an upper substrate ground trace for the path, and an upper substrate power trace providing an electrical path to the lower substrate surface via a substrate power via; a system printed circuit board including a power conductive path and an upper board surface having a ground plane; a solder ball array attached to said lower substrate surface, said solder ball array comprising a plurality of ground solder balls electrically connected to said ground plane and a plurality of power solder balls, each of the power solder balls being positioned opposite an adjacent ground solder ball to form a power/ground solder ball pair; and a chip mounted to the upper substrate surface.

In yet another embodiment, a semiconductor device includes: a substrate having an upper substrate surface, a lower substrate surface, and a perimeter defining the upper substrate surface and the lower substrate surface, the substrate The bottom further has an upper substrate ground trace providing an electrical path to a lower substrate ground trace on the lower substrate surface via a substrate ground via and an upper substrate ground trace providing an electrical path via a substrate power via to the lower substrate surface. upper substrate power traces of the electrical paths of the lower substrate power traces on the lower substrate surface; a system printed circuit board including an upper board surface having a ground plane, and a ground plane disposed adjacent to the ground plane a power plane, the upper board surface including a board ground trace electrically connected to the ground plane, the power ground plane further including a board power trace disposed opposite the board ground trace; a board attached to the An array of solder balls on the lower substrate surface, the array of solder balls includes a plurality of ground solder balls disposed in a plurality of outermost rows at the periphery of the substrate and attached to the ground plane, the array of solder balls further comprising a plurality of power solder balls electrically connected to the power plane, the plurality of power solder balls are arranged in a plurality of adjacent outer rows, and each outermost row is arranged between the periphery and a corresponding adjacent outer between rows; a chip mounted to the upper surface; a bond wire connecting the chip to the upper substrate ground trace; and a bond disposed on the upper board surface and electrically attached to the Decoupling capacitors for substrate ground traces.

In a further embodiment, a decoupling branch for attachment to a high speed chip includes: a decoupling capacitor; a first conductive path electrically connecting a chip ground terminal to the decoupling capacitor, the first A conductive path includes a ground bond wire, a substrate upper ground trace, a substrate ground via, a substrate lower ground trace, a ground solder ball, and a board ground trace; and a chip power The terminal is electrically connected to a second conductive path of the decoupling capacitor, the second conductive path includes a board power trace, a power solder ball, a substrate lower power trace, a substrate power via, a liner Bottom and upper power traces and a power bond wire.

In yet a further embodiment, a semiconductor device includes: a substrate having an upper substrate surface, a lower substrate surface, and a perimeter defining the upper and lower substrate surfaces, the upper substrate the surface further has at least one substrate upper power trace to provide an electrical path to at least one substrate lower power trace on said lower substrate surface via at least one substrate power via; a substrate attached to said lower substrate surface An array of solder balls on the lower substrate surface, the array of solder balls comprising a plurality of power solder balls disposed in an outermost row of the array and electrically connected to at least one substrate power via, the array of solder balls further comprising a set of a plurality of ground solder balls in adjacent outer rows of the array and electrically connected to a substrate ground via in the substrate; a system printed circuit board including an upper board surface having a power plane electrically connected to at least one of the plurality of power solder balls; and a chip mounted to the upper substrate surface.

In another embodiment, a wireless communication device having a high-speed, high-pin-count semiconductor device includes: a decoupling capacitor; path, the first conductive path includes a ground bond wire, a substrate upper ground trace, a substrate ground via, a substrate lower ground trace, a ground solder ball, and a board ground trace, wherein The board ground trace has a length of approximately one millimeter; and a second conductive path electrically connecting a semiconductor device power terminal to the decoupling capacitor, the second conductive path comprising a board power trace, a Power solder balls, a substrate lower power trace, a substrate power through hole, a substrate upper power trace, and a power bonding wire.

In a further embodiment, a semiconductor device includes: a solder ball array device for attaching a substrate to a system printed circuit board having a ground plane and a power supply trace, the solder ball array device is configured within a substrate perimeter; decoupling means connected between said ground plane and said power trace; and power/ground solder ball pair means disposed at said substrate perimeter for bonding said substrate A bottom electrode is attached to the decoupling member.

In yet a further embodiment, a method for powering a semiconductor device having a substrate attached to an upper surface of a system printed circuit board by means of an array of solder balls is disclosed, the method The method includes the steps of: (1) reducing the path length of a power signal by using a solder ball disposed at the periphery of a substrate as a ground solder ball to minimize signal parasitics; and (2) using a solder ball adjacent to the Solder balls with ground solder balls to form a power/ground solder ball pair for the power signal to minimize electromagnetic emissions.

In yet another embodiment, a method for powering a semiconductor device having a ball grid array includes: (1) utilizing a solder ball disposed at the periphery of a substrate as a ground solder ball to the steps of reducing the path length of a power signal to minimize signal parasitics; and (2) forming a power/ground solder ball pair for the power signal using a solder ball adjacent to the ground solder ball, and The step of minimizing electromagnetic emissions from said power signal.

These and other features, aspects and advantages of the present invention will be better understood with reference to the following drawings, descriptions and claims.

Description of drawings

1 is a partial cross-sectional view of a chip mounted on a substrate connected to a system printed circuit board through an array of solder balls according to an embodiment;

2 is a plan view of an array of solder balls on the lower surface of the substrate shown in FIG. 1 according to one embodiment;

3 is a schematic isometric view of an interconnect arrangement consisting of a semiconductor device including die bond wires, upper and lower substrate conductive traces, a board power trace located in a power plane, and a A board ground trace located in the ground plane within the system printed circuit board shown in Figure 1;

Figure 4 is a plan view of an alternative array of solder balls for the lower surface of the substrate shown in Figure 1;

5 is a schematic isometric view of an alternative interconnect configuration configuration of a semiconductor device including die bond wires, upper and lower substrate conductive traces, a board ground trace, and a board power trace ;and

FIG. 6 is a flowchart illustrating a method of providing power and ground connections for the semiconductor device shown in FIG. 3 that may be provided in accordance with one embodiment.

Detailed ways

The following detailed description is of the best mode currently contemplated for carrying out the embodiments of the invention. The description should not be taken in a limiting sense, but merely for the purpose of illustrating the general principles of embodiments of the invention, as the scope of the invention is best defined by the appended claims.

In summary, a high speed device is provided that has a signal path with low inductance characteristics that allow higher frequency signal and power transfer with minimal voltage drop and reduced electromagnetic emission. Such embodiments may include power/ground pin pairs positioned at the perimeter of the device to minimize voltage drop. In contrast, traditional high speed devices may provide power pins at or near the center of the device to use the outer pins for signals.

The embodiments may further include a substrate with vias of a minimum length to minimize voltage drop compared to the longer vias found in conventional substrates. A substrate with power and ground planes located near a substrate surface may also be included to reduce electromagnetic emissions compared to conventional multilayer substrates with internal power and ground planes. An example of an electronic device that could benefit from the application of the described embodiments is a handheld wireless communication device such as a mobile phone. However, it should be understood that the application of the disclosed embodiments is not limited to communication devices.

In general, the performance of power systems used in high speed semiconductor devices can be improved by reducing parasitics in the power systems. Printed circuit boards in traditional applications provide continuous, well-controlled power and ground planes to reduce these parasitics. However, since mobile electronic systems usually need to use high-density printed circuit boards, it is necessary to design the power and ground planes into multiple segmented areas. Such configurations can defeat the goal of minimizing the path length between the package pin and the decoupling capacitor.

In addition to reducing EMI by specifying an upper circuit board layer as a ground plane, embodiments may use board routing resources to reduce parasitics, rather than relying solely on power and ground plane configurations. For example, electronic packages can be designed using minimum wire lengths or flip-chip connections to minimize package inductance while achieving optimal pin placement and printed circuit board routing to coupling capacitors. Additionally, loop inductance can be minimized by placing power-ground solder ball pairs at the perimeter of the electronic package. Thus, the power-ground solder ball pairs can be connected to corresponding power and ground leads on the adjacent upper printed circuit board layer that are electrically connected to local decoupling capacitors. Mutual inductance can be reduced by connecting ground and power solder ball pairs to adjacent PCB layers, and via lengths can be minimized by providing connections to upper PCB layers.

An embodiment may be configured in a microprocessor package, such as a BGA, PGA, or chip scale package (CSP) suitable for use in, for example, palm-sized wireless communication devices. The use of BGA or PGA packages enables a complex integrated circuit to fit within a relatively small area on the system board of a wireless communication device. CSPs can provide a smaller device package with fewer pins than a BGA or PGA, but can utilize a power/ground pin pair configuration as described below. For high speed applications, the BGA configuration provides a lower inductance package than leaded configurations such as PGA.

Referring to FIGS. 1 , 2 and 3 , according to an embodiment, a semiconductor device 10 may include a chip 11 mounted to an upper substrate surface 12 of a substrate 13 and encapsulated within a chip package 15 . The semiconductor device 10 may further include a system printed circuit board 20 having a board ground trace 21 at an upper board surface 23, a power conductive path, such as a board ground trace Board power trace 25 in the layer below 21, and a dielectric layer 27 between board ground trace 21 and board power trace 25. Alternatively, the board ground trace 21 may form part of a board ground plane 63 covering part or all of the upper board surface 23 .

One or more ground bond wires 31 may be provided from chip 11 to an upper substrate ground trace 33 on substrate 13 . A substrate ground via 35 may be provided between a ground trace 33 of the upper substrate and a substrate lower ground trace 37 on the lower substrate surface 14 for electrical connection to the board via a ground solder ball 39. ground trace 21 . Likewise, one or more power bond wires 41 may be provided from chip 11 to an upper substrate power trace 43 on substrate 13 . A substrate power via 45 may be provided between a substrate upper power trace 43 and a substrate lower power trace 47 for electrical connection to the board power trace via a power solder ball 49 and a board power via 29 Line 25.

The semiconductor device 10 may further include a decoupling capacitor 51 on the upper board surface 23 . One end of decoupling capacitor 51 may be connected directly to board ground trace 21 as shown, while the other end of decoupling capacitor 51 may be connected to board power trace 25 through a second board power via 53 . Ground solder balls 39 may be located at a perimeter 19 of the substrate 13 . The perimeter 19 delimits the upper substrate surface 12 and the lower substrate surface 14 . This may allow the decoupling capacitor 51 to be placed within a distance "D" from the ground solder ball 39, where the distance "D" may be as small as 1 mm.

In the configuration shown, a cross-sectional area (referred to as "A") generally bounded by board ground trace 21, board power trace 25, board power via 29, and second board power via 53 may be smaller than conventional The corresponding cross-sectional area as seen in the design. Thus, as explained in more detail above, EMI generated by current flow within board power traces 25 (such as exemplified by the configuration shown in FIG. 1 ) may be less than EMI generated by current flow within conventional power traces.

The solder ball configuration shown in FIG. 2 may be used for semiconductor device 10 . An array of solder balls 55 may be attached to the lower substrate surface 14 of the substrate 13 . Array 55 may include a plurality of power solder balls 49 (i.e., circles shaded with intersecting parallel lines), each power solder ball 49 passing through a corresponding set of lower substrate power traces 47, substrate power vias 45 , and the power trace 43 on the upper part of the substrate is electrically connected to a corresponding power bond wire 41 (see FIG. 1 ). Array 55 may include a plurality of ground solder balls 39 (i.e., solid circles), each ground solder ball 39 passing through a corresponding set of substrate lower ground traces 37, substrate ground vias 35, and substrate upper ground traces. The wire 33 is electrically connected to a corresponding ground bonding wire 31 (see FIG. 1 ). Ground solder balls 39 may be located at the perimeter 19 of the substrate 13 . In the configuration shown, the ground solder balls 39 are located within one or more of the outermost rows 57a, 57b, 57c, and 57d.

Additionally, each power solder ball 49 can be paired with an adjacent ground solder ball 39 to reduce electromagnetic emissions from a conducted power signal. For example, a ground solder ball 39a and a power solder ball 49a may be connected to the same power source (not shown). Accordingly, ground solder ball 39a is positioned at perimeter 19 and power solder ball 49a is positioned adjacent to ground solder ball 39a to form a power/ground solder ball pair 50 (shown as a dashed box). When a power signal flows in (or out) through the ground solder ball 39a and out (or in) through the power solder ball 49a, the resulting power/signal may be generated due to the physical proximity of the ground solder ball 39a to the power solder ball 49a. Electromagnetic emissions from the grounded solder ball pair 50 are minimized. Accordingly, in the configuration shown, the power solder balls 49 are positioned within one or more adjacent outer rows 59a, 59b, 59c, and 59d. A plurality of solder balls 61 (ie, blank circles) are available for signal and other electrical connections.

Those skilled in the art will appreciate that while pins on the perimeter of a conventional substrate may typically be reserved for high speed signal paths, it is not necessary to route signals at or below 100 MHz to inside pins, such as signal ball 61. Timing issues can arise due to the increased signal path length.

As shown in FIG. 3, a decoupling branch 40 may include a first conductive path 40a from the chip ground terminal 16 to the decoupling capacitor 51, and a second conductive path 40b from the decoupling capacitor 51 to the chip power terminal 17. . The first conductive path 40a may include a ground bond wire 31 , a substrate upper ground trace 33 , a substrate ground via 35 , a lower substrate ground trace 37 , a ground solder ball 39 , and a board ground trace 21 . The length of the board ground trace 21 is approximately 1 mm. The second conductive path 40b may include board power traces 25 , power solder balls 49 , substrate lower power traces 47 , substrate power vias 45 , substrate upper power traces 43 , and power bond wires 41 . As shown in the illustration, board ground trace 21 is substantially the same width, shape, and location as board power trace 25 , and isolation is provided by dielectric layer 27 .

The configuration shown in Figures 1 and 3 can further provide electromagnetic shielding by using the ground plane 63 at the upper board surface 23 as an external ground and providing a power conductive path such as power plane 65 at the next inner layer Coupling routing of power signals. In addition, by using outer row pins for ground connections, such as ground solder balls 39 located in one or more of the outermost rows 57a, 57b, 57c, and 57d at the periphery 19 of the substrate 13, a device such as a decoupled The physical distance between a decoupling capacitor such as capacitor 51 and a corresponding pair of grounded solder balls 39 is minimized compared to conventional arrangements.

As is understood by those skilled in the art, high-speed signals are routed on the substrate surface of a printed circuit board, thereby generating EMI, and thus typically require a metal can or metallized plastic shield over the chip and substrate and shielded in phase. Adjacent to high-speed circuits (if any). By having power and ground at the surface and having board ground trace 21 opposite board power trace 25 (i.e., overlapping and separated by dielectric layer 27), electromagnetic shielding is "built in," as disclosed herein. , thereby reducing the need for external shielding. In a conventional configuration, power may be distributed through internal power planes. A chip with multiple power rails for power breakdown may require a system board with as many as eighteen layers when using such configurations. Providing power on or at a board surface layer (such as in the illustrated embodiment) may reduce the need for power vias and may also eliminate the need for power planes. This allows for easier board routing and enables a reduction in the number of substrate layers, resulting in cost savings.

Furthermore, by reducing parasitics in the disclosed embodiments, it is possible to improve the performance of the power supply that powers the semiconductor device 10 . For example, loop inductance may be reduced or minimized by using one or more power-ground solder ball pairs 50 disposed at the perimeter 19 of the semiconductor device 10 . Power solder balls 49 and ground solder balls 39 may preferably be connected on the system printed circuit board 20 to corresponding board power traces 25 and board ground traces 21 on adjacent upper layers that lead to local decoupling capacitors 51 . As understood by those skilled in the art, the effect of using adjacent layers in this manner is to provide mutual inductance, and using the upper layer for ground and power can minimize the length of the ground and power vias. In addition, EMI can be further reduced by designating an upper board layer as a ground plane.

In an alternate embodiment, the solder ball configuration shown in FIG. 4 may be used with semiconductor device 10 . An array of solder balls 70 may be attached to the lower substrate surface 14 of the substrate 13 . Array 70 includes a plurality of ground solder balls 71 (i.e., solid circles), each ground solder ball 71 accessible via a corresponding set of substrate lower ground traces 37, substrate ground vias 35, and substrate upper ground traces. Wire 33 is electrically connected to a corresponding ground bond wire 31 (see FIG. 1 ). Array 70 may include a plurality of power solder balls 73 (i.e., circles drawn with cross-section lines), each power solder ball 73 passing through a corresponding set of lower substrate power traces 47, substrate power vias 45, and substrate power vias 45. The bottom upper power trace 43 is electrically connected to a corresponding power bond wire 41 (see FIG. 1 ).

Power solder balls 73 may be located at perimeter 19 of substrate 13 . In the configuration shown, power solder balls 73 may be located in one or more outermost rows, such as outermost row 79a, and ground solder balls 71 may be located in one or more adjacent outer rows, such as adjacent outer row 79b. . Each power solder ball 73 can be paired with an adjacent ground solder ball 71 to form a power/ground solder ball pair 77 (indicated by a dashed box).

In yet another alternative embodiment, as shown in FIG. 5, a decoupling branch 80 may include a first conductive path 80a from a chip ground terminal (not shown) to the decoupling capacitor 51, and a first conductive path 80a from the decoupling capacitor 51. A second conductive path 80b to a chip power terminal (not shown). The first conductive path 80a may include a ground bonding wire 81, a substrate upper ground trace 83, a substrate ground via 85, a substrate lower ground trace 87, a ground solder ball 71, and a board ground. Trace 89. The second conductive path 80b may include a board power trace 99, power solder balls 73, a substrate lower power trace 97, a substrate power via 95, a substrate upper power trace 93, and a power Weld wire91. Decoupling capacitor 51 may be electrically connected to board ground trace 89 and board power trace 99 . As shown in FIG. 4 , power solder balls 73 may be located at perimeter 19 of substrate 13 .

Flowchart 100 in FIG. 6 shows a method for powering a semiconductor device having a substrate attached to the upper surface of a system printed circuit board by an array of solder balls. In step 101 , a ground solder ball (eg, ground solder ball 39 ) may be disposed within an array of solder balls at a perimeter of a substrate (eg, substrate 13 ). In step 103, a power solder ball (such as power solder ball 49) can be disposed adjacent to the ground solder ball in the solder ball array (such as solder ball array 55) to form a power/ground solder ball pair (such as power/ground solder ball pair). ground solder ball pair 50). In step 105, a ground plane (such as ground plane 63) may be provided in the upper surface of the system printed circuit board. In step 107, the ground solder balls may be attached to the ground plane. In step 109 , a power trace, such as board power trace 25 , may be disposed below the upper surface of the system printed circuit board. In step 111 , a dielectric layer, such as dielectric layer 27 , may be disposed between the power trace and the ground plane. In step 113, the power solder balls may be attached to the power traces. In step 115, a decoupling capacitor, such as decoupling capacitor 51, may be positioned adjacent to the ground solder ball, and in step 117, the decoupling capacitor may be positioned less than five millimeters from the ground solder ball , and preferably positioned within one millimeter from the ground solder ball. In a conventional configuration, the distance between the ground solder ball and the decoupling capacitor may be five millimeters or greater. As is understood by those skilled in the art, the methods described above also serve to minimize voltage drop and also reduce electromagnetic emissions.

It should be understood, of course, that the above description relates to various example embodiments and that modifications may be made without departing from the spirit and scope of the embodiments described in the claims below.

Claims (22)

1, a kind of semiconductor device, it comprises:

One substrate, it has:

One upper substrate surface, it has a upper substrate ground connection trace and a upper substrate power traces;

One bottom substrate surface, it has a bottom substrate ground connection trace, a bottom substrate power traces, and a periphery;

A substrate grounding through hole, it is electrically connected to described upper substrate ground connection trace with described lower substrate ground connection trace;

A substrate electric power through hole, it is electrically connected to described upper substrate power traces with described lower substrate power traces;

One is installed in the chip on described upper substrate surface, and described chip has one described chip is electrically connected to first bonding wire of described upper substrate ground connection trace, and described chip has one described chip is electrically connected to second bonding wire of described upper substrate power traces; And

One is attached to the solder ball array on described lower substrate surface, and described array comprises:

First group of solder ball, it is positioned at the position that directly is close to described periphery;

Second group of solder ball; And

One electric power/ground connection solder ball is right, it comprises: one is selected from described first group first ball and is selected from the second described second group ball, described first ball and described second ball directly are close to mutually, described first ball is electrically connected to described lower substrate ground connection trace, and described second ball is electrically connected to described lower substrate power traces.

2, semiconductor device as claimed in claim 1, it further comprises:

One system printed circuit board, it comprises that one has a upper board surface that is electrically connected to the ground plane of described first group of ball.

3, semiconductor device as claimed in claim 2, it further comprises the power supply conductivity path of being arranged to the direct next-door neighbour of described ground plane.

4, semiconductor device as claimed in claim 3, wherein said system printed circuit board further comprise a dielectric layer between described power supply conductivity path and described ground plane.

5, semiconductor device as claimed in claim 2, wherein said system printed circuit board comprises a decoupling capacitance.

6, semiconductor device as claimed in claim 5, wherein said decoupling capacitance is electrically connected to described ground plane.

7, a kind of semiconductor device, it comprises:

One substrate, it has a upper substrate surface, a bottom substrate surface, one upper substrate ground connection trace, described upper substrate ground connection trace provides a power path to described lower substrate surface via a substrate grounding through hole that directly is close to a substrate perimeter, and a upper substrate power traces, described upper substrate power traces provides a power path to described lower substrate surface via a substrate electric power through hole;

One system printed circuit board, it comprises that a power supply conductivity path and has the upper board surface of a ground plane;

One is attached to the solder ball array on described lower substrate surface, and described array comprises:

First group of solder ball, it is positioned at the position that directly is close to described periphery;

Second group of solder ball;

A plurality of electric power/ground connection solder ball is right, wherein each is to comprising: one is selected from described first group first ball and is selected from the second described second group ball, described first ball and described second ball directly are close to mutually, described first ball is electrically connected to described substrate grounding through hole, and described second ball is electrically connected to described substrate electric power through hole; And

One is installed in the chip on described upper substrate surface, and described chip has one described chip is electrically connected to the bonding wire of described upper substrate ground connection trace.

8, a kind of semiconductor device, it comprises:

One substrate, it has a upper substrate surface, one bottom substrate surface, an and periphery that defines described upper substrate surface and described lower substrate surface, described substrate further has a upper substrate ground connection trace, described upper substrate ground connection trace provides a power path to the lip-deep bottom substrate ground connection trace of described lower substrate via a substrate grounding through hole that is positioned at described periphery, and a upper substrate power traces, described upper substrate power traces provides a power path to the lip-deep bottom substrate power traces of described lower substrate via a substrate electric power through hole;

One system printed circuit board, it comprises that one has the power plane that the upper board surface is parallel with described ground plane with one and the next-door neighbour is provided with of a ground plane, described upper board surface comprises that one is electrically connected to the plate earthing trace of described ground plane, and described power plane further comprises a plate power trace that is oppositely arranged with described plate earthing trace;

One is attached to the solder ball array on described lower substrate surface, and described array comprises:

First group of solder ball, wherein each is positioned at the position that directly is close to described periphery;

Second group of solder ball;

A plurality of electric power/ground connection solder ball is right, wherein each is to comprising: one is selected from described first group first ball and is selected from the second described second group ball, described first ball and described second ball directly are close to mutually, described first ball is electrically connected to described lower substrate ground connection trace, and described second ball is electrically connected to described substrate electric power through hole; And

One is installed in the chip on described upper substrate surface;

One bonding wire, it is connected to described substrate grounding through hole via described upper substrate ground connection trace with described chip; And

One decoupling capacitance, it is arranged at described upper board surface and electricity is attached to described lower substrate ground connection trace.

9, semiconductor device as claimed in claim 8, wherein said decoupling capacitance electricity is attached to described power plane.

10, a kind of uncoupling branch that is suitable for being attached to a high-speed chip, described uncoupling branch comprises:

One decoupling capacitance;

One substrate, it has a substrate top surface, described substrate top surface has a upper substrate ground connection trace and a upper substrate power traces, described substrate has a substrate lower surface, described substrate lower surface has a bottom substrate ground connection trace and a bottom substrate power traces, and described substrate further comprises a periphery;

One first conductive path, it is electrically connected to described decoupling capacitance with a chip earth terminal, described first conductive path comprises that a ground connection bonding wire, a upper substrate ground connection trace, directly are close to the substrate grounding through hole of substrate perimeter, the ground connection solder ball that a bottom substrate ground connection trace, is set to directly be close to described periphery, and a plate earthing trace; And

One second conductive path, it is electrically connected to described decoupling capacitance with a chip power terminal, described second conductive path comprises a plate power trace, an electric power solder ball, a bottom substrate power traces, a substrate electric power through hole, a upper substrate power traces, and an electric power bonding wire, it is right to form one electric power/ground connection solder ball in described substrate perimeter that described electric power solder ball is arranged at the position that directly is close to described ground connection solder ball.

11, uncoupling as claimed in claim 10 branch, wherein said plate earthing trace comprises the length of millimeter one by one.

12, uncoupling as claimed in claim 10 branch, it comprises that further one is arranged on the dielectric layer between described plate earthing trace and the described plate power trace.

13, a kind of semiconductor device, it comprises:

One substrate, it has a upper substrate surface, a bottom substrate surface, an and periphery that defines described top and lower substrate surface, described upper substrate surface further has at least one upper substrate power traces, and described at least one upper substrate power traces provides a power path to lip-deep at least one the substrate bottom power traces of described lower substrate via at least one the substrate electric power through hole at described periphery place;

One is attached to the solder ball array on described lower substrate surface, described solder ball array comprises position and described periphery directly first group of solder ball and one second group of solder ball of next-door neighbour, it is right that described solder ball array has a plurality of electric power/ground connection solder ball, described each solder ball is selected from one first described first group ball and is selected from one second described second group ball comprising, described first ball and described second ball directly are close to mutually, described first ball is electrically connected to described substrate bottom power traces, and described second ball is electrically connected to a bottom substrate ground connection trace;

One system printed circuit board, it comprises a upper board surface, described upper board surface has at least one a power plane that is electrically connected in described a plurality of electric power solder ball; And

One is mounted to the chip on described upper substrate surface, and described chip comprises that one is electrically connected to the bonding wire of described at least one substrate electric power through hole with described chip.

14, a kind of have a wireless communication apparatus one high-speed, that high pin is counted semiconductor device, and described wireless communication apparatus comprises:

One decoupling capacitance device;

One first conductive path, it is electrically connected to described decoupling capacitance device with semiconductor device earth terminal, described first conductive path comprises the upper substrate ground connection trace, of a ground connection bonding wire, on a substrate directly substrate grounding through hole, a bottom substrate ground connection trace, a direct ground connection solder ball that is close to described periphery of the periphery of the described substrate of next-door neighbour, and a plate earthing trace, wherein said plate earthing trace comprises the length of millimeter one by one; And

One second conductive path, it is electrically connected to described decoupling capacitance device with semiconductor device power terminal, described second conductive path comprises a plate power trace, an electric power solder ball, a bottom substrate power traces, a substrate electric power through hole, a upper substrate power traces, and an electric power bonding wire, it is right to form one electric power/ground connection solder ball that described electric power solder ball is arranged at the position that directly is close to described ground connection solder ball.

15, wireless communication apparatus as claimed in claim 14, it comprises that further one is attached to the solder ball array of a bottom substrate surface of described substrate, described solder ball array comprises that one is arranged on the described periphery of direct next-door neighbour and is attached to the ground connection solder ball of described plate earthing trace, described solder ball array further comprises is arranged to the electric power solder ball that directly is close to described ground connection solder ball and is electrically connected to a power plane, and it is right that described ground connection solder ball and described electric power solder ball form one electric power/ground connection solder ball.

16, wireless communication apparatus as claimed in claim 15, wherein said plate earthing trace comprise one less than five millimeters length.

17, wireless communication apparatus as claimed in claim 14, it further comprises and is used for dielectric devices that a ground plane and described power trace are kept apart.

18, a kind of semiconductor device, it comprises:

The solder ball array apparatus, it is used for a substrate is attached to a system printed circuit board with a ground plane and a power trace, described solder ball array apparatus provides a plurality of electric power/ground connection solder ball right, and wherein each is to a ground connection solder ball that comprises a periphery that is arranged at the described substrate of direct next-door neighbour and an electric power solder ball that directly is close to described ground connection solder ball;

The bonding wire device, it is used for providing power path from a chip that is installed on the described substrate to a ground connection solder ball that is arranged at the described substrate perimeter of direct next-door neighbour; And

The uncoupling device, it is connected between described ground plane and the described power trace;

Wherein each electric power/ground connection solder ball is to providing the electric attaching of described substrate to described uncoupling device.

19, a kind of method that is used to semiconductor device power supply, described semiconductor device have one and are attached to the substrate of a upper face of a system printed circuit board by a solder ball array, and described method comprises the steps:

By utilizing a solder ball that is arranged on a periphery of the described substrate of direct next-door neighbour to reduce the path of an electric power signal, so that the signal parasitics minimizes as a ground connection solder ball;

Provide one from being installed in a chip on the described substrate to the power path of described ground connection solder ball, described power path comprises that a upper substrate ground connection trace and is arranged at the substrate grounding through hole of described periphery, and

By utilize one directly the electric power solder ball of the described ground connection solder ball of next-door neighbour form that one electric power/the ground connection solder ball is right so that electromagnetic emission minimizes.

20, method as claimed in claim 19, further comprising the steps: increases the electromagnetism shade by in the described upper face of described system printed circuit board a ground plane being set, so that electromagnetic emission minimizes.

21, a kind of method that is used to a semiconductor device with a ball grid array to power, described method comprises:

One utilizes a solder ball that is arranged on the periphery of direct next-door neighbour's one substrate to reduce the path of an electric power signal as a ground connection solder ball, with the step of minimum signal parasitics;

One provides one from being installed in a chip on the described substrate to the step of the grounding path of described ground connection solder ball, and

One utilizes one directly to be close to described ground connection solder ball and right as electric power/ground connection solder ball that a signal ball is used for described electric power signal with the solder ball of described ground connection solder ball coplane, so that from the minimized step of the electromagnetic emission of described electric power signal.

22, method as claimed in claim 21, its upper face that further comprises the steps: a system printed circuit board is set to a ground plane, and be parallel to and directly be close to described ground plane one power supply conductivity path is set, minimize so that be connected to the length of the through hole in described power supply conductivity path, make one thus by described ground plane, described power supply conductivity path reaches the area of section that described through hole defined and minimizes, to reduce the electromagnetic emission from described electric power signal.

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