CN105101638A - Method for decoupling circuit board and chip on circuit board - Google Patents
Method for decoupling circuit board and chip on circuit board Download PDFInfo
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- CN105101638A CN105101638A CN201510419771.9A CN201510419771A CN105101638A CN 105101638 A CN105101638 A CN 105101638A CN 201510419771 A CN201510419771 A CN 201510419771A CN 105101638 A CN105101638 A CN 105101638A
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
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Abstract
本发明提供一种电路板和电路板上芯片去耦的方法，该电路板包括：芯片、去耦电容、地层和电源层，其中，所述芯片中的第一引脚连接到所述去耦电容中的第二引脚，形成第一连接；所述芯片中的第三引脚与所述去耦电容中的第四引脚互联，形成第二连接；所述芯片中的第一引脚、所述去耦电容中的第二引脚还分别连接到与该第一引脚极性相同的地层和电源层中的第一方，以形成所述第一引脚和第二引脚在所述第一方中的第三连接；以形成所述第一连接与所述第三连接并联连接到第二连接的并联回路，有效地降低电路板中电路的寄生效应。
The invention provides a circuit board and a method for decoupling chips on the circuit board. The circuit board includes: a chip, a decoupling capacitor, a ground layer and a power layer, wherein the first pin in the chip is connected to the decoupling The second pin in the capacitor forms a first connection; the third pin in the chip is interconnected with the fourth pin in the decoupling capacitor to form a second connection; the first pin in the chip , the second pin of the decoupling capacitor is also respectively connected to the first side of the ground layer and the power layer with the same polarity as the first pin, so as to form a connection between the first pin and the second pin The third connection in the first party; to form a parallel loop in which the first connection and the third connection are connected in parallel to the second connection, effectively reducing the parasitic effect of the circuit in the circuit board.
Description
技术领域technical field
本发明涉及电子技术领域，特别涉及一种电路板和电路板上芯片去耦的方法。The invention relates to the field of electronic technology, in particular to a circuit board and a method for decoupling chips on the circuit board.
背景技术Background technique
电路板是所有电子设备中不可或缺的物理载体，早期的电路板，功能简单，器件密度小，信号速率很低，电路板能完成联通就可以实现。而随着人们对电子设备需求的变化，电子产品向着功能更加丰富，性能更加完美等方面发展，电路板上芯片去耦是保证电路板正常工作的关键之一。目前，对电路板上芯片的去耦主要是芯片引脚与去耦电容的引脚连接或者芯片引脚与去耦电容的引脚通过过孔分别与对应的电源层或地层连接，使得电路板中电路具有较高的寄生效应。The circuit board is an indispensable physical carrier in all electronic equipment. The early circuit boards had simple functions, small device density, and low signal rate. The circuit board can complete the Unicom. With the change of people's demand for electronic equipment, electronic products are developing towards richer functions and more perfect performance. The decoupling of chips on the circuit board is one of the keys to ensure the normal operation of the circuit board. At present, the decoupling of the chips on the circuit board is mainly to connect the chip pins to the pins of the decoupling capacitor or to connect the chip pins and the pins of the decoupling capacitor to the corresponding power layer or ground layer respectively through via holes, so that the circuit board Medium circuits have high parasitic effects.
发明内容Contents of the invention
本发明提供一种电路板和电路板上芯片去耦的方法，以降低电路板中电路的寄生效应。The invention provides a circuit board and a method for decoupling chips on the circuit board to reduce the parasitic effect of the circuit in the circuit board.
一种电路板，包括：芯片、去耦电容、地层和电源层，其中，A circuit board, including: a chip, a decoupling capacitor, a ground layer and a power layer, wherein,
所述芯片中的第一引脚连接到所述去耦电容中的第二引脚，形成第一连接；A first pin in the chip is connected to a second pin in the decoupling capacitor to form a first connection;
所述芯片中的第三引脚与所述去耦电容中的第四引脚互联，形成第二连接；The third pin in the chip is interconnected with the fourth pin in the decoupling capacitor to form a second connection;
所述芯片中的第一引脚、所述去耦电容中的第二引脚还分别连接到与该第一引脚极性相同的地层和电源层中的第一方，以形成所述第一引脚和第二引脚在所述第一方中的第三连接；The first pin in the chip and the second pin in the decoupling capacitor are also respectively connected to the ground layer with the same polarity as the first pin and the first side in the power layer to form the first pin a third connection of a pin and a second pin in said first party;
以形成所述第一连接与所述第三连接并联连接到第二连接的并联回路。to form a parallel loop in which the first connection and the third connection are connected in parallel to the second connection.
优选地，所述芯片中的第一引脚为距离所述去耦电容最近的引脚；Preferably, the first pin in the chip is the pin closest to the decoupling capacitor;
所述去耦电容中的第二引脚为距离所述芯片最近的引脚。The second pin of the decoupling capacitor is the closest pin to the chip.
优选地，所述芯片中的第一引脚具体通过连接线或预先铺设的导通介质连接到所述去耦电容中的第二引脚。Preferably, the first pin in the chip is connected to the second pin in the decoupling capacitor through a connection wire or a pre-laid conduction medium.
优选地，所述芯片中的第一引脚连接到所述第一方中的第一过孔；Preferably, a first pin in said chip is connected to a first via in said first side;
所述去耦电容中的第二引脚连接到所述第一方中的第二过孔。A second pin in the decoupling capacitor is connected to a second via in the first side.
优选地，所述芯片中的第三引脚具体通过连接线或预先铺设的导通介质与所述去耦电容中的第四引脚互联；Preferably, the third pin in the chip is specifically interconnected with the fourth pin in the decoupling capacitor through a connection wire or a pre-laid conduction medium;
或者，or,
所述芯片中的第三引脚、所述去耦电容中的第四引脚分别具体通过过孔与该第三引脚极性相同的地层和电源层中的第二方连接，以形成所述芯片中的第三引脚与所述去耦电容中的第四引脚互联。The third pin in the chip and the fourth pin in the decoupling capacitor are respectively connected to the ground layer with the same polarity as the third pin and the second party in the power layer through holes to form the The third pin in the chip is interconnected with the fourth pin in the decoupling capacitor.
优选地，所述第一引脚和所述第二引脚为地引脚；所述第三引脚和所述第四引脚为电源引脚；Preferably, the first pin and the second pin are ground pins; the third pin and the fourth pin are power pins;
所述第一方为地层。The first party is a formation.
优选地，所述第一引脚和所述第二引脚为电源引脚；所述第三引脚和所述第四引脚为地引脚；Preferably, the first pin and the second pin are power supply pins; the third pin and the fourth pin are ground pins;
所述第一方为电源层。The first party is a power layer.
一种电路板上芯片去耦的方法，包括：A method for chip decoupling on a circuit board, comprising:
将所述芯片中的第一引脚连接到所述去耦电容中的第二引脚，以形成第一连接；connecting a first pin in the chip to a second pin in the decoupling capacitor to form a first connection;
将所述芯片中的第三引脚连接到所述去耦电容中的第四引脚，以形成第二连接；connecting a third pin in the chip to a fourth pin in the decoupling capacitor to form a second connection;
将所述芯片中的第一引脚、所述去耦电容中的第二引脚分别连接到与该第一引脚极性相同的地层和电源层中的第一方，以形成所述第一引脚和第二引脚在所述第一方中的第三连接；Connect the first pin in the chip and the second pin in the decoupling capacitor to the ground layer and the first side of the power layer with the same polarity as the first pin, respectively, to form the first pin a third connection of a pin and a second pin in said first party;
以形成所述第一连接与所述第三连接并联连接到第二连接的并联回路。to form a parallel loop in which the first connection and the third connection are connected in parallel to the second connection.
优选地，所述芯片中的第一引脚为距离所述去耦电容最近的引脚；Preferably, the first pin in the chip is the pin closest to the decoupling capacitor;
所述去耦电容中的第二引脚为距离所述芯片最近的引脚。The second pin of the decoupling capacitor is the closest pin to the chip.
优选地，所述芯片中的第一引脚连接到所述第一方中的第一过孔；Preferably, a first pin in said chip is connected to a first via in said first side;
所述去耦电容中的第二引脚连接到所述第一方中的第二过孔。A second pin in the decoupling capacitor is connected to a second via in the first side.
本发明实施例提供了一种电路板和电路板上芯片去耦的方法，该电路板包括：芯片、去耦电容、地层和电源层，其中，所述芯片中的第一引脚连接到所述去耦电容中的第二引脚，形成第一连接；所述芯片中的第三引脚与所述去耦电容中的第四引脚互联，形成第二连接；所述芯片中的第一引脚、所述去耦电容中的第二引脚还分别连接到与该第一引脚极性相同的地层和电源层中的第一方，以形成所述第一引脚和第二引脚在所述第一方中的第三连接；以形成所述第一连接与所述第三连接并联连接到第二连接的并联回路，该并联回路有效地降低电路板中电路的寄生效应。Embodiments of the present invention provide a circuit board and a method for decoupling chips on the circuit board. The circuit board includes: a chip, a decoupling capacitor, a ground layer, and a power layer, wherein the first pin of the chip is connected to the The second pin in the decoupling capacitor forms a first connection; the third pin in the chip is interconnected with the fourth pin in the decoupling capacitor to form a second connection; the second pin in the chip One pin and the second pin in the decoupling capacitor are also respectively connected to the ground layer with the same polarity as the first pin and the first side in the power layer to form the first pin and the second pin a third connection of the pins in said first side; to form a parallel loop of said first connection and said third connection being connected in parallel to the second connection, the parallel loop effectively reducing parasitic effects of circuits in the circuit board .
附图说明Description of drawings
图1为本发明实施例提供的一种电路板的结构示意图；Fig. 1 is a schematic structural diagram of a circuit board provided by an embodiment of the present invention;
图2为本发明另一实施例提供的一种电路板的结构示意图；Fig. 2 is a schematic structural diagram of a circuit board provided by another embodiment of the present invention;
图3为本发明又一实施例提供的一种电路板的结构示意图；Fig. 3 is a schematic structural diagram of a circuit board provided by another embodiment of the present invention;
图4为本发明实施例提供的一种电路板上芯片去耦的方法流程图。FIG. 4 is a flowchart of a method for decoupling chips on a circuit board according to an embodiment of the present invention.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
如图1所示，本发明实施例提供的一种电路板，包括：芯片、去耦电容、地层和电源层，其中，As shown in FIG. 1, a circuit board provided by an embodiment of the present invention includes: a chip, a decoupling capacitor, a ground layer, and a power layer, wherein,
所述芯片101中的第一引脚1011连接到所述去耦电容102中的第二引脚1021，形成第一连接；The first pin 1011 in the chip 101 is connected to the second pin 1021 in the decoupling capacitor 102 to form a first connection;
所述芯片101中的第三引脚1012与所述去耦电容102中的第四引脚1022互联，形成第二连接；The third pin 1012 in the chip 101 is interconnected with the fourth pin 1022 in the decoupling capacitor 102 to form a second connection;
所述芯片101中的第一引脚1011、所述去耦电容102中的第二引脚1021还分别连接到与该第一引脚极性相同的地层和电源层中的第一方103，以形成所述第一引脚和第二引脚在所述第一方中的第三连接；The first pin 1011 in the chip 101 and the second pin 1021 in the decoupling capacitor 102 are respectively connected to the ground layer and the first side 103 in the power layer with the same polarity as the first pin, to form a third connection of the first pin and the second pin in the first party;
以形成所述第一连接与所述第三连接并联连接到第二连接的并联回路。to form a parallel loop in which the first connection and the third connection are connected in parallel to the second connection.
由于减少回路的面积，也可以有效地使寄生效应导致的影响降低，上述实施例中所述芯片101中的第一引脚1011为距离所述去耦电容最近的引脚，所述去耦电容102中的第二引脚1021，为距离所述芯片最近的引脚；另外，由于第一引脚可以为芯片的地引脚，也可以为芯片的电源引脚，在本发明又一实施例中，按照第一引脚类型的不同，将电路板分为两类：Since the area of the loop is reduced, the influence caused by parasitic effects can also be effectively reduced. In the above embodiment, the first pin 1011 in the chip 101 is the pin closest to the decoupling capacitor, and the decoupling capacitor The second pin 1021 in 102 is the pin closest to the chip; in addition, since the first pin can be the ground pin of the chip or the power pin of the chip, in another embodiment of the present invention According to the difference of the first pin type, the circuit board is divided into two categories:
在第一类电路板中，如图2所示，芯片101中第一引脚为芯片的地引脚2011，第三引脚为芯片的电源引脚2012，该芯片101中地引脚2011为距离去耦电容最近的引脚，且去耦电容102的第二引脚为去耦电容的地引脚2021，也为距离该芯片最近的引脚，去耦电容102的第四引脚为去耦电容的电源引脚2022；In the first type of circuit board, as shown in Figure 2, the first pin in the chip 101 is the ground pin 2011 of the chip, the third pin is the power supply pin 2012 of the chip, and the ground pin 2011 in the chip 101 is The pin closest to the decoupling capacitor, and the second pin of the decoupling capacitor 102 is the ground pin 2021 of the decoupling capacitor, which is also the pin closest to the chip, and the fourth pin of the decoupling capacitor 102 is the ground pin 2021 of the decoupling capacitor. The power supply pin 2022 of the coupling capacitor;
芯片101中芯片地引脚2011通过连接线或预先铺设的导通介质连接到所述去耦电容102中去耦电容地引脚2021；The chip ground pin 2011 in the chip 101 is connected to the decoupling capacitor ground pin 2021 in the decoupling capacitor 102 through a connecting wire or a pre-laid conduction medium;
芯片地引脚2011和去耦电容地引脚2021还分别通过过孔连接到所述地层203；The chip ground pin 2011 and the decoupling capacitor ground pin 2021 are also respectively connected to the ground layer 203 through via holes;
芯片电源引脚2012与去耦电容电源引脚2022分别具体通过过孔连接到电源层204。The chip power pin 2012 and the decoupling capacitor power pin 2022 are respectively connected to the power layer 204 through via holes.
在第二类电路板中，如图3所示，芯片101中第一引脚为芯片的电源引脚3011，第三引脚为芯片的地引脚3012，该芯片101中电源引脚3011为距离去耦电容最近的引脚，且去耦电容102的第二引脚为去耦电容的电源引脚3021，也为距离该芯片最近的引脚，去耦电容102的第四引脚为去耦电容的地引脚3022；In the second type circuit board, as shown in Figure 3, the first pin in the chip 101 is the power pin 3011 of the chip, the third pin is the ground pin 3012 of the chip, and the power pin 3011 in the chip 101 is The pin closest to the decoupling capacitor, and the second pin of the decoupling capacitor 102 is the power supply pin 3021 of the decoupling capacitor, which is also the pin closest to the chip, and the fourth pin of the decoupling capacitor 102 is the decoupling capacitor. The ground pin 3022 of the coupling capacitor;
芯片101中芯片电源引脚3011通过连接线或预先铺设的导通介质连接到所述去耦电容102中去耦电容电源引脚3021；The chip power supply pin 3011 in the chip 101 is connected to the decoupling capacitor power supply pin 3021 in the decoupling capacitor 102 through a connecting wire or a pre-laid conduction medium;
芯片电源引脚3011和去耦电容电源引脚3021还分别通过过孔连接到所述电源层303；The chip power supply pin 3011 and the decoupling capacitor power supply pin 3021 are also respectively connected to the power supply layer 303 through via holes;
芯片地引脚2012与去耦电容地引脚2022分别具体通过过孔连接到地层304。The chip ground pin 2012 and the decoupling capacitor ground pin 2022 are respectively connected to the ground layer 304 through via holes.
在本发明又一实施例中，在第一类电路板中，芯片电源引脚2012与去耦电容电源引脚2022互联的方式为：In yet another embodiment of the present invention, in the first type of circuit board, the chip power supply pin 2012 is interconnected with the decoupling capacitor power supply pin 2022 in the following manner:
芯片电源引脚具体通过连接线或预先铺设的导通介质与去耦电容电源引脚互联。The power supply pin of the chip is specifically interconnected with the power supply pin of the decoupling capacitor through a connection wire or a pre-laid conduction medium.
在本发明又一实施例中，在第二类电路板中，芯片地引脚2012与去耦电容的地引脚2022互联的方式为：In yet another embodiment of the present invention, in the second type of circuit board, the chip ground pin 2012 is interconnected with the ground pin 2022 of the decoupling capacitor in the following manner:
芯片地引脚具体通过连接线或预先铺设的导通介质与去耦电容地引脚互联。Specifically, the ground pin of the chip is interconnected with the ground pin of the decoupling capacitor through a connection wire or a pre-laid conduction medium.
在本发明又一实施例中，在第二类电路板中，芯片地引脚2012与去耦电容的地引脚2022互联的方式为：In yet another embodiment of the present invention, in the second type of circuit board, the chip ground pin 2012 is interconnected with the ground pin 2022 of the decoupling capacitor in the following manner:
芯片地引脚、去耦电容地引脚分别具体通过过孔连接到地层。The ground pin of the chip and the ground pin of the decoupling capacitor are respectively connected to the ground plane through via holes.
如图4所示，本发明实施例提供一种电路板上芯片去耦的方法，该方法可以包括如下步骤：As shown in FIG. 4, an embodiment of the present invention provides a method for decoupling chips on a circuit board, and the method may include the following steps:
步骤401：将所述芯片中的第一引脚连接到所述去耦电容中的第二引脚，以形成第一连接；Step 401: Connect a first pin in the chip to a second pin in the decoupling capacitor to form a first connection;
步骤402：将所述芯片中的第三引脚连接到所述去耦电容中的第四引脚，以形成第二连接；Step 402: Connect the third pin in the chip to the fourth pin in the decoupling capacitor to form a second connection;
步骤403：将所述芯片中的第一引脚、所述去耦电容中的第二引脚分别连接到与该第一引脚极性相同的地层和电源层中的第一方，以形成所述第一引脚和第二引脚在所述第一方中的第三连接；Step 403: Connect the first pin in the chip and the second pin in the decoupling capacitor to the ground layer and the first side of the power layer with the same polarity as the first pin, respectively, to form a third connection of said first pin and said second pin in said first party;
步骤404：以形成所述第一连接与所述第三连接并联连接到第二连接的并联回路。Step 404: To form a parallel loop in which the first connection and the third connection are connected in parallel to the second connection.
在本发明一个实施例中，为了能够减少回路的面积，以使寄生效应导致的影响减小，步骤401和步骤403中所述芯片中的第一引脚为距离所述去耦电容最近的引脚；所述去耦电容中的第二引脚为距离所述芯片最近的引脚，而步骤403的具体实施方式：所述芯片中的第一引脚连接到所述第一方中的第一过孔；所述去耦电容中的第二引脚连接到所述第一方中的第二过孔。In one embodiment of the present invention, in order to reduce the area of the loop and reduce the influence caused by parasitic effects, the first pin in the chip in step 401 and step 403 is the pin closest to the decoupling capacitor. pin; the second pin in the decoupling capacitor is the pin closest to the chip, and the specific implementation of step 403: the first pin in the chip is connected to the first pin in the first party a via hole; the second pin in the decoupling capacitor is connected to the second via hole in the first side.
由于上述实施例中芯片中的第一引脚可以为地引脚，也可以为电源引脚，那么，Since the first pin in the chip in the above embodiment can be a ground pin or a power pin, then,
当芯片中的第一引脚可以为地引脚时，该电路板上芯片去耦的方式：When the first pin in the chip can be the ground pin, the chip decoupling method on the circuit board:
将所述芯片中的地引脚具体通过连接线或预先铺设的导通介质连接到所述去耦电容中的第二引脚，该所述去耦电容中的第二引脚即成为去耦电容的地引脚，而且该芯片中的地引脚为距离去耦电容最近的引脚，该去耦电容的地引脚为距离芯片最近的引脚，使得连接线路尽可能短，以减少寄生效应；Connect the ground pin in the chip to the second pin in the decoupling capacitor through a connection wire or a pre-laid conduction medium, and the second pin in the decoupling capacitor becomes a decoupling capacitor. The ground pin of the capacitor, and the ground pin of the chip is the pin closest to the decoupling capacitor, and the ground pin of the decoupling capacitor is the pin closest to the chip, so that the connection line is as short as possible to reduce parasitic effect;
将所述芯片中的电源引脚连接到所述去耦电容中的第四引脚，该去耦电容中的第四引脚即成为去耦电容的电源引脚；在这一过程中，所述芯片中的电源引脚具体通过连接线或预先铺设的导通介质与所述去耦电容中的电源引脚互联；或者，所述芯片中的电源引脚、所述去耦电容中的电源引脚分别具体通过过孔与电源层连接，以形成所述芯片中的电源引脚与所述去耦电容中的电源引脚互联；Connect the power supply pin in the chip to the fourth pin in the decoupling capacitor, and the fourth pin in the decoupling capacitor becomes the power supply pin of the decoupling capacitor; in this process, all The power supply pins in the chip are specifically interconnected with the power supply pins in the decoupling capacitor through a connecting wire or a pre-laid conduction medium; or, the power supply pins in the chip, the power supply in the decoupling capacitor The pins are respectively connected to the power supply layer through via holes, so as to form the interconnection between the power supply pins in the chip and the power supply pins in the decoupling capacitor;
将所述芯片中的地引脚、所述去耦电容中的地引脚分别通过过孔的方式连接到地层；Connecting the ground pin in the chip and the ground pin in the decoupling capacitor to the ground layer through via holes;
以形成并联回路。而该并联回路可以大大降低寄生效应。to form a parallel circuit. And the parallel loop can greatly reduce the parasitic effect.
当芯片中的第一引脚可以为电源引脚时，该电路板上芯片去耦的方式：When the first pin in the chip can be a power supply pin, the chip decoupling method on the circuit board:
将所述芯片中的电源引脚具体通过连接线或预先铺设的导通介质连接到所述去耦电容中的第二引脚，该所述去耦电容中的第二引脚即成为去耦电容的电源引脚，而且该芯片中的电源引脚为距离去耦电容最近的引脚，该去耦电容的电源引脚为距离芯片最近的引脚，使得连接线路尽可能短，以减少寄生效应；Connect the power supply pin in the chip to the second pin in the decoupling capacitor through a connection wire or a pre-laid conduction medium, and the second pin in the decoupling capacitor becomes a decoupling capacitor. The power supply pin of the capacitor, and the power supply pin of the chip is the pin closest to the decoupling capacitor, and the power supply pin of the decoupling capacitor is the pin closest to the chip, so that the connection line is as short as possible to reduce parasitic effect;
将所述芯片中的地引脚连接到所述去耦电容中的第四引脚，该去耦电容中的第四引脚即成为去耦电容的地引脚；在这一过程中，所述芯片中的地引脚具体通过连接线或预先铺设的导通介质与所述去耦电容中的地引脚互联；或者，所述芯片中的地引脚、所述去耦电容中的地引脚分别具体通过过孔与地层连接，以形成所述芯片中的地引脚与所述去耦电容中的地引脚互联；Connect the ground pin in the chip to the fourth pin in the decoupling capacitor, and the fourth pin in the decoupling capacitor becomes the ground pin of the decoupling capacitor; in this process, all The ground pin in the chip is specifically interconnected with the ground pin in the decoupling capacitor through a connecting wire or a pre-laid conduction medium; or, the ground pin in the chip, the ground pin in the decoupling capacitor The pins are respectively connected to the ground layer through via holes, so as to form the interconnection between the ground pin in the chip and the ground pin in the decoupling capacitor;
将所述芯片中的地引脚、所述去耦电容中的地引脚分别通过过孔的方式连接到地层；Connecting the ground pin in the chip and the ground pin in the decoupling capacitor to the ground layer through via holes;
以形成并联回路。而该并联回路可以大大降低寄生效应。to form a parallel circuit. And the parallel loop can greatly reduce the parasitic effect.
上述实施例至少可以达到如下有益效果：The foregoing embodiments can at least achieve the following beneficial effects:
1.电路板包括：芯片、去耦电容、地层和电源层，其中，所述芯片中的第一引脚连接到所述去耦电容中的第二引脚，形成第一连接；所述芯片中的第三引脚与所述去耦电容中的第四引脚互联，形成第二连接；所述芯片中的第一引脚、所述去耦电容中的第二引脚还分别连接到与该第一引脚极性相同的地层和电源层中的第一方，以形成所述第一引脚和第二引脚在所述第一方中的第三连接；以形成所述第一连接与所述第三连接并联连接到第二连接的并联回路，该并联回路有效地降低电路板中电路的寄生效应。1. The circuit board includes: a chip, a decoupling capacitor, a ground layer and a power layer, wherein the first pin in the chip is connected to the second pin in the decoupling capacitor to form a first connection; the chip The third pin in the decoupling capacitor is interconnected with the fourth pin in the decoupling capacitor to form a second connection; the first pin in the chip and the second pin in the decoupling capacitor are also respectively connected to The first side of the ground layer and the power layer with the same polarity as the first pin to form a third connection between the first pin and the second pin in the first side; to form the first pin A connection is connected in parallel with said third connection to a parallel return of the second connection, the parallel return being effective for reducing parasitic effects of circuits in the circuit board.
2.所述芯片中的第一引脚为距离所述去耦电容最近的引脚，所述去耦电容中的第二引脚为距离所述芯片最近的引脚。使得并联回路的面积最小，也进一步降低了寄生效应，而寄生效应的降低，可以使去耦效果增强，去耦效果的增强可有效地提高芯片的稳定性和可靠性。2. The first pin in the chip is the pin closest to the decoupling capacitor, and the second pin in the decoupling capacitor is the pin closest to the chip. The area of the parallel circuit is minimized, and the parasitic effect is further reduced, and the reduction of the parasitic effect can enhance the decoupling effect, and the enhanced decoupling effect can effectively improve the stability and reliability of the chip.
3.芯片与电容引脚间的连接可以通过连接线或预先铺设的导通介质连接，同时，还能通过过孔的方式分别连接到底层或电源层以实现芯片与电容引脚间的连接，这种设计增强了电路板的灵活性及实用性。3. The connection between the chip and the capacitor pin can be connected through a connecting wire or a pre-laid conductive medium. At the same time, it can also be connected to the bottom layer or the power layer through a via hole to realize the connection between the chip and the capacitor pin. This design enhances the flexibility and practicality of the circuit board.
需要说明的是，在本文中，诸如第一和第二之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个〃〃〃〃〃〃”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同因素。It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or sequence. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a """""" does not exclude the presence of additional same elements in the process, method, article or apparatus comprising said element.
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明保护的范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the present invention. within the scope of protection.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106294996A (en) * | 2016-08-09 | 2017-01-04 | 浪潮电子信息产业股份有限公司 | A kind of circuit decoupling method and a kind of decoupling circuit |
| CN109688694A (en) * | 2018-12-29 | 2019-04-26 | 北京行易道科技有限公司 | Circuit structure and device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1926684A (en) * | 2004-06-07 | 2007-03-07 | 富士通株式会社 | Capacitor built-in semiconductor device and method for manufacturing same |
| CN1938850A (en) * | 2004-02-24 | 2007-03-28 | 高通股份有限公司 | Optimized power delivery to high speed, high pin-count devices |
| CN101653050A (en) * | 2007-02-06 | 2010-02-17 | 新美亚通讯设备有限公司 | The localized distributive capacitance that is used for the enhancing of circuit board |
| JP4668132B2 (en) * | 2005-06-22 | 2011-04-13 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Printed circuit board with built-in RF module power stage circuit |
| CN104576583A (en) * | 2013-10-18 | 2015-04-29 | 北大方正集团有限公司 | Power supply chip, printed circuit board and manufacturing method of printed circuit board |
-
2015
- 2015-07-16 CN CN201510419771.9A patent/CN105101638A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1938850A (en) * | 2004-02-24 | 2007-03-28 | 高通股份有限公司 | Optimized power delivery to high speed, high pin-count devices |
| CN1926684A (en) * | 2004-06-07 | 2007-03-07 | 富士通株式会社 | Capacitor built-in semiconductor device and method for manufacturing same |
| JP4668132B2 (en) * | 2005-06-22 | 2011-04-13 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Printed circuit board with built-in RF module power stage circuit |
| CN101653050A (en) * | 2007-02-06 | 2010-02-17 | 新美亚通讯设备有限公司 | The localized distributive capacitance that is used for the enhancing of circuit board |
| CN104576583A (en) * | 2013-10-18 | 2015-04-29 | 北大方正集团有限公司 | Power supply chip, printed circuit board and manufacturing method of printed circuit board |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106294996A (en) * | 2016-08-09 | 2017-01-04 | 浪潮电子信息产业股份有限公司 | A kind of circuit decoupling method and a kind of decoupling circuit |
| CN106294996B (en) * | 2016-08-09 | 2019-08-02 | 浪潮电子信息产业股份有限公司 | A kind of circuit decoupling method and a kind of decoupling circuit |
| CN109688694A (en) * | 2018-12-29 | 2019-04-26 | 北京行易道科技有限公司 | Circuit structure and device |
| CN109688694B (en) * | 2018-12-29 | 2024-03-22 | 北京行易道科技有限公司 | Circuit structure and device |
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