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NL2000656A1 - Werkwijze en systeem voor het splitsen van een patroonlayout. - Google Patents

Werkwijze en systeem voor het splitsen van een patroonlayout.

Info

Publication number
NL2000656A1
NL2000656A1 NL2000656A NL2000656A NL2000656A1 NL 2000656 A1 NL2000656 A1 NL 2000656A1 NL 2000656 A NL2000656 A NL 2000656A NL 2000656 A NL2000656 A NL 2000656A NL 2000656 A1 NL2000656 A1 NL 2000656A1
Authority
NL
Netherlands
Prior art keywords
splitting
pattern layout
layout
pattern
Prior art date
Application number
NL2000656A
Other languages
English (en)
Other versions
NL2000656C2 (nl
Inventor
Jaw-Jung Shin
King-Chang Shu
Tsai-Sheng Gau
Burn-Jeng Lin
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of NL2000656A1 publication Critical patent/NL2000656A1/nl
Application granted granted Critical
Publication of NL2000656C2 publication Critical patent/NL2000656C2/nl

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
NL2000656A 2007-02-06 2007-05-22 Werkwijze en systeem voor het splitsen van een patroonlayout. NL2000656C2 (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US67186607 2007-02-06
US11/671,866 US7934177B2 (en) 2007-02-06 2007-02-06 Method and system for a pattern layout split

Publications (2)

Publication Number Publication Date
NL2000656A1 true NL2000656A1 (nl) 2008-08-07
NL2000656C2 NL2000656C2 (nl) 2009-06-23

Family

ID=39677257

Family Applications (1)

Application Number Title Priority Date Filing Date
NL2000656A NL2000656C2 (nl) 2007-02-06 2007-05-22 Werkwijze en systeem voor het splitsen van een patroonlayout.

Country Status (3)

Country Link
US (1) US7934177B2 (nl)
CN (1) CN101241517B (nl)
NL (1) NL2000656C2 (nl)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5032948B2 (ja) 2006-11-14 2012-09-26 エーエスエムエル マスクツールズ ビー．ブイ． Ｄｐｔプロセスで用いられるパターン分解を行うための方法、プログラムおよび装置
US8028253B2 (en) * 2007-04-02 2011-09-27 Synopsys, Inc. Method and apparatus for determining mask layouts for a multiple patterning process
US8453107B2 (en) * 2008-11-14 2013-05-28 Microsoft Corporation Diagram layout patterns
KR101828492B1 (ko) * 2010-10-13 2018-03-29 삼성전자 주식회사 패턴 형성 방법, 레티클, 및 패턴 형성 프로그램이 기록된 기록 매체
US8671368B1 (en) * 2010-12-29 2014-03-11 Cadence Design Systems, Inc. Method, system, and program product to implement detail routing for double pattern lithography
US8375348B1 (en) 2010-12-29 2013-02-12 Cadence Design Systems, Inc. Method, system, and program product to implement colored tiles for detail routing for double pattern lithography
US8560998B1 (en) 2010-12-29 2013-10-15 Cadence Design Systems, Inc. Method, system, and program product to implement C-routing for double pattern lithography
US8775977B2 (en) * 2011-02-15 2014-07-08 Taiwan Semiconductor Manufacturing Co., Ltd Decomposition and marking of semiconductor device design layout in double patterning lithography
US8359556B1 (en) 2011-06-29 2013-01-22 International Business Machines Corporation Resolving double patterning conflicts
US8516403B2 (en) * 2011-09-01 2013-08-20 International Business Machines Corporation Multiple patterning layout decomposition for ease of conflict removal
US8434033B2 (en) 2011-09-01 2013-04-30 International Business Machines Corporation Mask assignment for multiple patterning lithography
US9152039B2 (en) * 2011-10-18 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple patterning technology method and system for achieving minimal pattern mismatch
US9003349B1 (en) 2013-06-28 2015-04-07 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing a physical electronic design with area-bounded tracks
US9117052B1 (en) 2012-04-12 2015-08-25 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patterns
US8984465B1 (en) 2013-06-28 2015-03-17 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for automatically assigning track patterns to regions for physical implementation of an electronic design
US9251299B1 (en) 2013-06-28 2016-02-02 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for associating track patterns with rules for electronic designs
US9183343B1 (en) 2012-08-31 2015-11-10 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs
US9104830B1 (en) 2013-06-28 2015-08-11 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design
US9213793B1 (en) 2012-08-31 2015-12-15 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing electronic designs using flexible routing tracks
US9817941B2 (en) 2012-12-04 2017-11-14 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs
US9141752B2 (en) * 2013-03-14 2015-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. EDA tool and method for conflict detection during multi-patterning lithography
US8914755B1 (en) * 2013-05-28 2014-12-16 Taiwan Semiconductor Manufacturing Company Limited Layout re-decomposition for multiple patterning layouts
US9165103B1 (en) 2013-06-28 2015-10-20 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for tessellating and labeling routing space for routing electronic designs
US20150097249A1 (en) * 2013-10-04 2015-04-09 Globalfoundries Inc. Cross coupling gate using mulitple patterning
US9026971B1 (en) * 2014-01-07 2015-05-05 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-patterning conflict free integrated circuit design
CN104166303B (zh) * 2014-08-06 2018-01-09 京东方科技集团股份有限公司 一种掩膜板和曝光方法
US10339249B2 (en) * 2016-03-29 2019-07-02 Synopsys, Inc. Using color pattern assigned to shapes for custom layout of integrated circuit (IC) designs
US10192021B1 (en) * 2017-02-21 2019-01-29 Cadence Design Systems, Inc. Generating and inserting metal and metal etch shapes in a layout to correct design rule errors
CN113126422B (zh) * 2021-03-01 2022-11-29 上海华力集成电路制造有限公司 改善金属线工艺热点的opc修正方法
CN114638189A (zh) * 2022-03-16 2022-06-17 东方晶源微电子科技（北京）有限公司 一种解决掩模版着色边界冲突的方法、装置和计算机设备

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3406506B2 (ja) * 1997-03-24 2003-05-12 シャープ株式会社 フォトマスクのパターン補正方法およびフォトマスクのパターン補正装置
US7494749B2 (en) * 2000-02-04 2009-02-24 Advanced Micro Devices, Inc. Photolithography using interdependent binary masks
US6653026B2 (en) * 2000-12-20 2003-11-25 Numerical Technologies, Inc. Structure and method of correcting proximity effects in a tri-tone attenuated phase-shifting mask
US6541166B2 (en) 2001-01-18 2003-04-01 International Business Machines Corporation Method and apparatus for lithographically printing tightly nested and isolated device features using multiple mask exposures
JP4746753B2 (ja) * 2001-03-05 2011-08-10 ルネサスエレクトロニクス株式会社 荷電粒子線露光用マスクの形成方法および荷電粒子線用マスクを形成するためのパターンデータの処理プログラム
TWI301229B (en) * 2002-03-25 2008-09-21 Asml Masktools Bv Method and apparatus for decomposing semiconductor device patterns into phase and chrome regions for chromeless phase lithography
SG118239A1 (en) * 2003-04-24 2006-01-27 Asml Netherlands Bv Lithographic processing method and device manufactured thereby
JP4617272B2 (ja) * 2005-04-12 2011-01-19 エーエスエムエル マスクツールズ ビー．ブイ． 二重露光リソグラフィを実行するための方法、プログラム製品及びデバイス製造方法
US7310797B2 (en) * 2005-05-13 2007-12-18 Cadence Design Systems, Inc. Method and system for printing lithographic images with multiple exposures
US8132130B2 (en) * 2005-06-22 2012-03-06 Asml Masktools B.V. Method, program product and apparatus for performing mask feature pitch decomposition for use in a multiple exposure process
US7493589B2 (en) * 2005-12-29 2009-02-17 Asml Masktools B.V. Method, program product and apparatus for model based geometry decomposition for use in a multiple exposure process
JP5032948B2 (ja) * 2006-11-14 2012-09-26 エーエスエムエル マスクツールズ ビー．ブイ． Ｄｐｔプロセスで用いられるパターン分解を行うための方法、プログラムおよび装置

Also Published As

Publication number Publication date
CN101241517A (zh) 2008-08-13
US7934177B2 (en) 2011-04-26
CN101241517B (zh) 2010-06-23
NL2000656C2 (nl) 2009-06-23
US20080189672A1 (en) 2008-08-07

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Date Code Title Description
AD1A A request for search or an international type search has been filed
RD2N Patents in respect of which a decision has been taken or a report has been made (novelty report)

Effective date: 20090422

PD2B A search report has been drawn up