NL1030431C2 - Bias current generator for integrated circuit device, has proportional-to-absolute-temperature current generator with exclusively transistors that generates current that is proportional to operating temperature - Google Patents

Abstract

The generator has a proportional-to-absolute-temperature current generator (200) with exclusively transistors that generates a current that is proportional to operating temperature. An inverse-proportional-to-absolute-temperature current generator has an exclusive transistor that generates a current that is inversely proportional to the operating temperature. A summing circuit sums the currents to generate a bias current.

Description

Brief indication: Resistant bias current generating circuit.

The present invention relates generally to an integrated circuit device, and more particularly to a bias current generating circuit for an integrated circuit device.

Bias current generating circuits are commonly used in integrated circuit devices to generate bias current based on an external supply voltage. An ideal bias current generating circuit generates a constant bias current that is independent of variation in power input, process parameters, and temperature. A conventional bias current generating circuit is described in

U.S. Patent 6,203,436, the contents of which are incorporated herein by reference. Such a circuit uses a first current generator in which a first generated current is proportional to the absolute temperature (PTAT), or increases with increased temperature, and a second current generator in which a second generated current is inversely proportional to the absolute temperature (IPTAT) , or decreases with increased temperature. The first and second generated currents are added to generate a combined bias current with reduced responsiveness to variation in temperature and power input.

In the conventional design, as discussed in US 5,604,427 and US 5,990,727, the PTAT and IPTAT power generators use a resistor to generate the respective first and second currents. Since resistors are very responsive to process variation and operating temperature variation, the resulting bias current is just as responsive to process and temperature variations in the conventional approach.

The present invention is directed to a bias current generating circuit that generates a reliable and consistent bias current, regardless of the variation in power input, process, and temperature.

In particular, in one embodiment, the bias current generator according to the present invention generates a bias current using a PTAT current generator and an IPTAT 35 current generator comprising only active circuit elements, for example transistors. No passive elements, such as resistors, are used. The generated bias current is essentially a function of the respective ratios of transistors of current paths of the device. In this way the responsiveness of the resulting generated bias current to variations in supplied power, process and temperature is greatly reduced.

In one aspect, the present invention relates to a bias current generator. The generator comprises a proportional-to-the-absolute-temperature (PTAT) current generator which comprises only active circuit elements and which generates a first current which is proportional to the operating temperature. A inversely proportional to the absolute temperature (IPTAT) current generator comprising only active circuit elements generates a second current which is inversely proportional to the operating temperature. An adder circuit adds the first and second currents to generate a bias current.

In one embodiment, the bias current is generated substantially independently of the operating temperature.

In another embodiment, the PTAT power generator comprises: a PMOS cascode current mirror comprising: a first PMOS transistor and a second PMOS transistor connected in series between a first reference voltage and a first node, a gate of the first PMOS transistor being coupled to the first node, and a gate of the second PMOS transistor is coupled to a first bias voltage; and a third PMOS transistor and a fourth PMOS transistor connected in series between the first reference voltage and a second node, wherein a gate of a third PMOS transistor is coupled to the first node and a gate of the fourth PMOS transistor is coupled to the first setting voltage; an NMOS cascode stream mirror comprising; a first NMOS transistor and a second NMOS transistor connected in series between the first node and the third node, a gate of the first NMOS transistor being coupled to a second bias voltage and a gate of the second NMOS transistor being coupled to the second node; and a third NMOS transistor and a fourth NMOS transistor connected in series between the second node and a fourth node, a gate of the third NMOS transistor being coupled to the second bias voltage and a gate of the fourth NMOS transistor being coupled to the second 40 node; a first diode connected in series between the third node and a second reference voltage; and a second diode connected in series between the fourth node and the second reference voltage.

In another embodiment, the first reference voltage comprises a power supply voltage and the second reference voltage comprises a ground voltage.

In another embodiment, the first diode comprises a PNP-type bipolar junction transistor, an emitter of which is connected to the third node and whose base and collector are connected to the second reference voltage and the second diode a PNP-type bipolar junction transistor includes an emitter connected to the fourth node and a base and collector connected to the second reference voltage.

In another embodiment, the first bias voltage 15 is at a voltage level sufficient to saturate the second and fourth PMOS transistors, and wherein the second bias voltage is at a voltage level sufficient to saturate the first and third NMOS transistors.

In another embodiment, the IPTAT power generator comprises: 20. a fifth PMOS transistor and a sixth PMOS transistor connected in series between the first reference voltage and a fifth node, a gate of the fifth PMOS transistor being coupled to the first node and a gate of the sixth PMOS transistor is coupled to the first bias voltage; and a fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the second reference voltage, the fifth and sixth NMOS transistors each being configured in a diode configuration; a seventh PMOS transistor connected between the first reference voltage and a sixth node, the gate of the seventh PMOS transistor being coupled to the sixth node; and a seventh NMOS transistor and an eighth NMOS transistor connected in series between the sixth node and the second reference voltage, a gate of the seventh NMOS transistor being coupled to the second node, and a gate of the eighth NMOS transistor being coupled with the fifth node.

In another embodiment, the addition circuit comprises: an eighth PMOS transistor and a ninth PMOS transistor connected in series between the first reference voltage and a seventh node, a gate of the eighth PMOS transistor being coupled to the first node and a gate of the ninth PMOS

- 4 - transistor is coupled to the first bias voltage; a tenth PMOS transistor connected between the first reference voltage and the seventh node, a gate of the tenth PMOS transistor being coupled to the sixth node; a ninth NMOS transistor connected between the seventh node and the second reference voltage, the ninth NMOS transistor gate being coupled to the seventh node; and a tenth NMOS transistor connected between a bias node where the bias current is drawn and the second reference voltage, the gate of the tenth NMOS transistor being coupled to the seventh node.

In another embodiment, the bias current generator further comprises a bias voltage generator that includes a first bias voltage generator that generates the first bias voltage and a second bias generator that generates the second bias voltage. The first bias voltage generator comprises: an eleventh PMOS transistor and an eleventh NMOS transistor that are in series between the first reference voltage and the second reference voltage, the gate of the eleventh PMOS transistor being coupled to the first node, the gate of the eleventh NMOS transistor is coupled with a

20. connection between the eleventh PMOS transistor and the eleventh NMOS

transistor; a twelfth PMOS transistor and a twelfth NMOS transistor in series between the first reference voltage and the second reference voltage, the gate of the twelfth PMOS transistor being coupled to one connection between the twelfth PMOS transistor and the twelfth NMOS transistor, the gate of the twelfth NMOS transistor is coupled to the port of the eleventh NMOS transistor; and a thirteenth PMOS transistor, a fourteenth PMOS transistor and a thirteenth NMOS transistor that are in series between the first reference voltage and the second reference voltage, wherein the gate of the thirteenth PMOS transistor is coupled to the gate of the twelfth PMOS transistor, the gate of the fourteenth PMOS transistor is coupled to a connection between the fourteenth PMOS transistor and the thirteenth NMOS transistor, the gate of the thirteenth NMOS transistor being coupled to the gate of the twelfth NMOS transistor, the connection of the fourteenth PMOS transistor and the thirteenth NMOS transistor provides the first bias voltage. The second bias voltage generator comprises: a fifteenth PMOS transistor and a fifteenth NMOS transistor in series between the first reference voltage and an eighth 40 node, the gate of the fifteenth PMOS transistor being coupled to the first node, the gate of the fifteenth NMOS transistor is coupled to a connection between the fifteenth NMOS transistor and the fifteenth NMOS transistor; a sixteenth PMOS transistor, a fourteenth NMOS transistor and one.

5 sixteenth NMOS transistor in series between the first reference voltage and the eighth node, the gate of the sixteenth NMOS transistor being coupled to the first node PMOS transistor and the fourteenth NMOS transistor, the gate of the sixteenth NMOS transistor being coupled to the gate of the fifteenth. 10 NMOS transistor; and a third diode is connected in series between the eighth node and the second reference voltage, the connection of the sixteenth PMOS transistor and the fourteenth NMOS transistor providing the second bias voltage.

In another embodiment, the third diode comprises a PNP-15 type bipolar junction transistor, an emitter of which is connected to the eighth node and whose base and collector are connected to the second reference voltage.

In another embodiment, the bias current generator further comprises a start-up circuit which ensures that the transistors in the PTAT current generator and the IPTAT current generator initialize beyond a degenerate setting.

In another embodiment, the boot circuit comprises: a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth NMOS transistor and a twentieth NMOS transistor connected in series between the first reference voltage and the second reference voltage, the gates of the seventeenth and eighteenth PMOS transistors are each coupled to the second reference voltage, a gate of the nineteenth NMOS transistor being coupled to the second bias voltage and a gate of the twentieth NMOS transistor being coupled to the second node; a seventeenth NMOS transistor connected in series between the first node and the second reference voltage; and an eighteenth NMOS transistor connected in series between the first bias voltage and the second reference voltage.

In another embodiment, the adder circuit comprises: a first current mirror that generates a first mirrored current in response to the first current generated by the PTAT; a second current mirror that generates a second mirrored current in response to a second current generated by the PTAT; and a - 6 - third current mirror that generates a bias current based on the sum of the first mirrored current and the second mirrored current.

In another embodiment, the first current is further generated as a function of a first dimension ratio of at least one transistor along a first current path with respect to a second dimension ratio of at least one transistor along a second current path / the second current path and the first current path in a current mirror configuration, wherein the first and second dimension ratios for corresponding transistors in the first 10 and second current paths are different.

In another embodiment, the second current is further generated as a function of a voltage that is generated in the PTAT current generator that is shared by an active circuit element in the IPTAT current generator for generating the second current.

In another embodiment, the PTAT current generator comprises: a first current path comprising a number of transistors; and a second current path comprising a number of transistors, wherein at least one of the number of transistors of the second current path corresponds to one of the number of transistors of the first current path, wherein at least one pair of the corresponding transistors of the first and second current path has a different dimension ratio, the first current being generated in response to the different dimension ratio of the corresponding transistors of the first and second current paths.

In another embodiment, the IPTAT current generator comprises: a third current path comprising a plurality of transistors, the second current being generated as a function of a voltage generated in the PTAT current generator that is shared by a transistor in the third current path for the generating the second stream.

In another embodiment, the PTAT current generator comprises: a first diode connected in series with a first reference voltage and a third node; a second diode connected in series between the first reference voltage and a fourth node; a PMOS cascode stream mirror comprising: a first PMOS. transistor and a second PMOS transistor connected in series between the third node and the first node, and a third PMOS transistor and a fourth PMOS transistor connected in series between the fourth node and a second node; wherein the - 7 - ports of the first and third PMOS transistors are coupled to the second node, and the ports of the second and fourth PMOS transistors are coupled to a first bias voltage; and an NMOS cascade current mirror comprising: a first NMOS transistor and a second NMOS transistor connected in series between the first node and a second reference voltage, and a third NMOS transistor and a fourth NMOS transistor connected in series between the second node and the second reference voltage, with ports of the first and third NMOS transistors coupled to a second bias voltage, and ports of the second and fourth NMOS. transistors are coupled to the first node.

In another embodiment, the first reference voltage comprises a supply voltage, the second reference voltage comprises a ground voltage.

In another embodiment, the first diode comprises an NPN-type bipolar junction transistor, an emitter of which is connected to the third node and whose base and collector are connected to the first reference voltage and the second diode comprises an NPN-type bipolar junction transistor, of which an emitter is connected to the fourth node and of which a base and collector are connected to the first reference voltage.

In another embodiment, the first bias voltage is at a voltage level sufficient to saturate the second and fourth PMOS transistors, the second bias voltage being at a voltage level sufficient to saturate the first and third NMOS transistors.

In another embodiment, the IPTAT current generator comprises: a fifth PMOS transistor and a sixth PMOS transistor connected in series between the first reference voltage and a fifth node, the fifth and sixth PMOS transistors each being configured in a diode configuration; and a fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the second reference voltage, a gate of the fifth NMOS transistor being coupled to the second bias voltage and a gate of the sixth NMOS transistor being coupled to the first node; a seventh PMOS transistor and an eighth PMOS transistor connected in series between the first reference voltage and a sixth node, with a gate of the seventh PMOS transistor coupled to the fifth node, and a 40 gate of the eighth PMOS transistor coupled to the second 8 node; and a seventh NMOS transistor connected between the sixth node and the second reference voltage, the gate of the seventh NMOS transistor being coupled to the sixth node.

In another embodiment, the addition circuit comprises: an eighth NMOS transistor and a ninth NMOS transistor connected in series between a seventh node and the second reference voltage, a gate of the eighth NMOS transistor being coupled to the second bias voltage and a gate of the ninth NMOS transistor is coupled to the first node; a tenth NMOS transistor connected between the seventh node and the second reference voltage, a gate of the tenth NMOS transistor coupled to the sixth node; and a ninth PMOS transistor connected between the first reference voltage and the seventh node, the gate of the ninth PMOS transistor being coupled to the seventh node; and a tenth PMOS transistor connected between the first reference voltage and a bias node on which the bias current is drawn, the gate of the tenth NMOS transistor being coupled to the seventh node.

In another aspect, the present invention relates to a bias current generator. A proportional-to-the-absolute-temperature (PTAT) current generator generates a first current which is proportional to the operating temperature. The PTAT current generator comprises a first current path comprising a number of transistors; and a second current path comprising a number of transistors, wherein at least one of the number of transistors of the second current path corresponds to one of the number of transistors of the first current path, wherein at least one pair of the corresponding transistors of the first and second current paths have a different size ratio, the first current being generated in response to a different size ratio of the corresponding transistors of the first and second current paths. A reverse-proportional-to-the-absolute-temperature (IPTAT) current generator generates a second current that is inversely proportional to the operating temperature. The IPTAT 35 current generator comprises a third current path comprising a number of transistors. The second current is generated as a function of a voltage generated in the PTAT current generator that is shared by a transistor in the third current path for generating the second current. An adder circuit adds the first and second 40 currents to generate a bias current.

- 9 -

In one embodiment, the PTAT power generator comprises only active circuit elements.

In another embodiment, the IPTAT power generator comprises only active switching elements.

In another embodiment, the bias current is generated substantially independently of the operating temperature.

In another embodiment, the PTAT power generator comprises: a PMOS cascode current mirror comprising: a first PMOS transistor and a second PMOS transistor connected in series between a first reference voltage and a first node, a gate of the first PMOS transistor being coupled to the first node and a gate of the second PMOS transistor is coupled to a first bias voltage; and a third PMOS transistor and a fourth PMOS transistor connected in series between the first reference voltage and a second node, a gate of the third PMOS transistor being coupled to the first node and a gate of the fourth PMOS transistor being coupled to the first bias voltage; an NMOS cascade current mirror comprising: a first NMOS transistor and a second NMOS transistor connected in series between the first node and a third node, a gate of the first NMOS transistor being coupled to the second bias voltage and a gate of the second NMOS transistor is coupled to the second node; and a third NMOS transistor and a fourth NMOS transistor connected in series between the second node and a fourth node, a gate of the third NMOS transistor being coupled to the second bias voltage and a gate of the fourth NMOS transistor being coupled to the second node; wherein a first diode is connected in series between the third node and a second reference voltage; and a second diode 30 connected in series between the fourth node and the second reference voltage.

In another embodiment, the first reference voltage comprises a power source voltage and the second reference voltage comprises a ground voltage.

In another embodiment, the first diode comprises a PNP-type bipolar junction transistor, an emitter of which is connected to the third node and whose base and collector are connected to the second reference voltage and the second diode comprises a PNP-type bipolar junction transistor, of which an emitter is connected to the fourth node and of which a base and collector are connected to the second reference voltage.

In another embodiment, the first bias voltage is at a voltage level sufficient to saturate the second and fourth PMOS transistors, and wherein the second bias voltage is at a voltage level sufficient to saturate the first and third NMOS transistors.

In another embodiment, the IPTAT power generator comprises: a fifth PMOS transistor and a sixth PMOS transistor connected in series between the first reference voltage and a fifth node, a gate of the fifth PMOS transistor being coupled to the first node and a gate of the sixth PMOS transistor is coupled to the first bias voltage; and a fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the second reference voltage, wherein the fifth and the sixth NMOS transistors are each configured in a diode configuration; a seventh PMOS transistor connected between the first reference voltage and a sixth node, the gate of the seventh PMOS transistor 20 being coupled to the sixth node; and a seventh NMOS transistor and an eighth NMOS transistor connected in series between the sixth node and the second reference voltage, a gate of the seventh NMOS transistor being coupled to the second node, and a gate of the eighth NMOS transistor being coupled to the 25th node.

In another embodiment, the addition circuit comprises: an eighth PMOS transistor and a ninth PMOS transistor connected in series between the first reference voltage and a seventh node, a gate of the eighth PMOS transistor being coupled to the first node and a gate of the ninth PMOS

transistor is coupled to the first bias voltage; a tenth PMOS transistor connected between the first reference voltage and the seventh node, a gate of the tenth PMOS transistor being coupled to the sixth node; a ninth NMOS.

A transistor connected between the seventh node and the second reference voltage, the ninth NMOS transistor gate being coupled to the seventh node; and a tenth NMOS transistor connected between a set node at which the set current is drawn and the second reference voltage, the gate of the tenth NMOS transistor being coupled to the seventh node.

- 11 -

In another embodiment, the bias current generator further comprises a first bias voltage generator that generates the first bias voltage and a second bias voltage generator that generates the second bias voltage. The first bias voltage generator 5 comprises: an eleventh PMOS transistor and an eleventh NMOS transistor in series between the first reference voltage and the second reference voltage, the gate of the eleventh PMOS transistor being coupled to the first node, the gate of the eleventh NMOS transistor is coupled to a connection between the eleventh PMOS transistor and the eleventh NMOS transistor; a twelfth PMOS transistor and a twelfth NMOS transistor in series between the first reference voltage and the second reference voltage, the gate of the twelfth PMOS transistor being coupled to a connection between the twelfth PMOS transistor and the twelfth NMOS transistor, the gate of the twelfth NMOS transistor is coupled to the port of the eleventh NMOS transistor; and a thirteenth PMOS transistor, a fourteenth PMOS transistor and a thirteenth NMOS transistor that is in series between the first reference voltage and the second reference voltage, the gate of the thirteenth PMOS transistor 20 being coupled to the gate of the twelfth PMOS transistor, the gate of the fourteenth PMOS transistor is coupled to a connection between the fourteenth PMOS transistor and the thirteenth PMOS transistor, the gate of the thirteenth NMOS transistor being coupled to the gate of the twelfth NMOS transistor, the connection of the fourteenth PMOS transistor and the thirteenth NMOS transistor provides the first bias voltage. The second bias current generator comprises: a fifteenth PMOS transistor and a fifteenth NMOS transistor that is in series between the first reference voltage and an eighth node, the gate of the fifteenth PMOS transistor being coupled to the first node,

wherein the gate of the fifteenth NMOS transistor is coupled to a connection between the fifteenth PMOS transistor and the fifteenth NMOS transistor; a sixteenth PMOS transistor, a fourteenth NMOS transistor and a sixteenth NMOS transistor that is in series between the first reference voltage and the eighth node, the gate of the sixteenth PMOS transistor being coupled to the first node, the gate of the fourteenth NMOS transistor is coupled to a connection between the sixteenth PMOS transistor and the fourteenth NMOS transistor, the gate of the sixteenth NMOS 40 transistor being coupled to the gate of the fifteenth NMOS

12 transistor; and a third diode connected in series between the eighth node and the second reference voltage, the connection of the sixteenth PMOS transistor and the fourteenth NMOS transistor providing the second bias voltage.

In another embodiment, the third diode comprises a PNP-type bipolar junction transistor, an emitter of which is connected to the eighth node and of which a base and collector are connected to the second reference voltage.

In another embodiment, the bias current generator 10 further comprises a startup circuit which ensures that transistors in the PTAT current generator and the IPTAT current generator initialize beyond a degenerate setting.

In another embodiment, the boot circuit comprises: a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth NMOS transistor and a twentieth NMOS transistor connected in series between the first reference voltage and the second reference voltage, the gates of the seventeenth and eighteenth PMOS transistors are each coupled to the second reference voltage, a gate of the nineteenth NMOS transistor being coupled to the second bias voltage and the gate of the twentieth NMOS transistor being coupled to the second node; a seventeenth NMOS transistor connected in series between the first node and the second reference voltage; and an eighteenth NMOS transistor connected in series between the first bias voltage and the second reference voltage.

In another embodiment, the adder circuit comprises: a first current mirror that generates a first mirrored current in response to the first current generated by the PTAT; a second current mirror that generates a second mirrored current in response to a second current generated by the PTAT; and a third current mirror that generates the bias current based on the sum of the first mirrored current and the second mirrored current.

In another embodiment, the first current is further generated as a function of a first dimension ratio of at least one transistor along a first current path with respect to a second dimension ratio of at least one transistor along a second current path, the second current path and the first current path in a current mirror configuration, wherein the first and second dimension ratios for corresponding transistors in the first 40 and second current paths are different.

- 13 -

In another embodiment, the second current is further generated as a function of a voltage that is generated in the PTAT current generator that is divided by an active circuit element in the IPTAT current generator for generating the second current.

Brief description of the drawing

The foregoing and other objects, features and advantages of the invention will be apparent from the more specific description of the preferred embodiments of the invention, as shown in the accompanying drawing, in which like reference numerals refer to like parts in different views. The drawings are not necessarily to scale, the emphasis is instead on the representation of the principles of the invention.

FIG. 1 is a circuit diagram of a first embodiment of a bias current generating circuit according to the present invention.

FIG. 2 is a circuit diagram of a second embodiment of a bias current generating circuit according to the present invention.

FIG. 3 is a circuit diagram of a third embodiment of a bias current generating circuit according to the present invention.

FIG. 1 is a circuit diagram of a first embodiment of a bias current generating circuit in accordance with the present invention. Referring to FIG. 1, the bias current generating circuit comprises a proportional-to-absolute-temperature (PTAT) -current generator 200, a proportional-to-absolute-temperature (IPTAT) -current generator 400, and an adder circuit 500. In In one embodiment, the PTAT current generator 200 and the IPTAT current generator 400 use only active elements, such as NMOS and PMOS transistors and bipolar junction transistors, and therefore do not contain passive elements, such as resistors. The PTAT power generator 200 generates a first sub stream IJ that is proportional to the temperature.

The IPTAT power generator 400 generates a second sub-current I2 which is inversely proportional to the temperature. The adder circuit 500 adds the first sub-current I2 and the second sub-current I2 to generate a sum current I3 35 which is used to generate a bias current I2. Since the PTAT current generator 200 and the IPTAT current generator 400 have no passive elements such as resistors 1, the bias current generating circuit of FIG. 1 is substantially inadmissible for process variation, applied voltage, and temperature.

- 14 -

In this embodiment, the PTAT power generator 200 includes a PMOS cascade current mirror 211, an NMOS cascade current mirror 220, and first and second PNP-type bipolar junction transistors 210, 209.

The PMOS cascade current mirror 211 comprises a first PMOS transistor-208 and a second PMOS transistor 206 connected in series between a first reference voltage VDD and a first node 240. The PMOS cascode current mirror 211 further comprises a third PMOS transistor 207 and a fourth PMOS transistor 205 connected in series between the first reference voltage VDD and a second node 242. Gates of the first PMOS transistor 208 and the third PMOS

transistor 207 are coupled to the first node 240. Gates of the second PMOS transistor 206 and the fourth PMOS transistor 205 are coupled to a first bias voltage V ^ sp.

The NMOS cascade current mirror 220 comprises a first NMOS transistor 204 and a second NMOS transistor 202 connected in series between the first node 240 and a third node 244. The NMOS cascade current mirror 220 further comprises a third NMOS transistor 203 and a fourth NMOS transistor 201 coupled in series between the second node 242 and a fourth node 206. Gates of the first NMOS transistor 204 and the third NMOS transistor 203 are coupled to a second bias voltage Vcasn. Ports of the second NMOS transistor 202 and the fourth NMOS transistor 201 are coupled to the second node 242.

A first bipolar junction transistor 210 is coupled in a diode configuration between the third node 244 and a second reference voltage GND. The base of the first bipolar junction transistor 210 is coupled to the second reference voltage GND. A second bipolar junction transistor 209 is coupled in a diode configuration between the fourth node 246 and the second reference voltage GND. The base of the second bipolar junction transistor 209 is coupled to the second reference voltage GND.

Thanks to the operation of the current-current mirror configuration, the first sub-current I3 flowing through the first and second PMOS transistors 208 and 206 and the first and second NMOS transistors 204 and 202 is equal to the first mirror sub-current I3 'passing through the third and fourth PMOS transistors 207 and 205 and the third and fourth NMOS transistors 203 and 201 are flowing. According to the circuit configuration, the voltages of the gates of the third and fourth NMOS 40 transistors 202, 201 are the same, therefore:

Vbel + Vgs201 = Vbe2 + Vgs202 (1) in which the voltage on the fourth node V ^ is the base-emitter voltage of the second bipolar junction transistor 209, Vgs20i is the gate source voltage of the fourth NMOS transistor 201, the voltage on the third node, ν ^ 2 is the base-emitter voltage of the first bipolar junction transistor 210 and Vgs202 is the gate source voltage of the third NMOS transistor 202.

10 Since the base-emitter voltage of a bipolar junction transistor can be represented as:

1st

Vbe = VT -Ln - (2)

Is 15 where VT represents the thermal voltage, Ie is the collector current through the transistor and Is is the bipolar junction transistor saturation current, and since the gate source voltage of a MOS transistor 20 can be represented as: V -J ΦD, ύτ (3)

Ves V nncm (w / L) Vth 25 where Ia is the drain current, μη is the electron mobility, Cox is the port unit capacity, W / L is the dimension ratio of the transistor and Vu, the transistor threshold voltage, can then, with neglect of the base current, the equations (2) and (3) above are substituted in equation (1) with the result: 30 Υτ'1η iL + i ¢, cm lw / ΕΓ ^ * Vaa 35 = V7 "to lL> * i C» <.W / L) "* (4)

If the transistor body effect is considered negligible, and the threshold voltage of the fourth NMOS transistor is assumed to be equal to the threshold voltage of the third NMOS transistor,

Vth201 = Vth202t and the first substroom Jj is considered to be equal to the first mirrored substroom li ', Ij = Ii', then equation (4) can be rewritten as: v 1. 7sao I Hl II (mT ^ T, 5,

Vt Isz »1 U„ Ca (WZDjmIï <W / L) m 1)

With regard to flow Ij: I® · t * p. 2 U „c“ (W / L) s0, • lnm) / l = 2 (^ - 1) 2 (6) where k is the Boltzman constant, T is the absolute temperature, m = 15 IS210 / Is209 / gf the electron charge value and n = (W / L) 201 / (W / L) 202. The parameter p 'Cox is proportional to T'1'5, and thus the first subcurrent is proportional to T0.5, Ix% T0.5, and in particular in the operating range of the bias circuit, in particular in the industrial temperature range between -55 ° C and 125 ° C, the proportional ratio is linear. In an embodiment, both m and n are chosen to be greater than 1 and, in an example, n = 2 and m = 7.

The gate voltage Vgn of the fourth NMOS transistor 201 is used to generate the second subcurrent I2 at the IPTAT current generator 400, and can be represented as the sum of the base-emitter voltage of the second bipolar junction transistor 209, V and the gate source voltage of the fourth NMOS transistor 201, Vga20i. Substitution of equation (3) provides: V gn ~~ V be 1+ ^ fls201 = Vbtl + fl μ 'Cm (WIL) 201 + V * λε _ rr r / C7 * lil / 77 (7) - 17 -

Returning to equation (2), thereby differentiating Vbej with respect to the absolute temperature T provides: d V bubble __ d VT Fr dl C209 BV τ I r 9 / S2Q9 5 ar ar ar ar 1075209/8 ar ar )

If the base current of the second bipolar junction transistor 209 is considered negligible and not taken into account, the current flowing through the second bipolar junction transistor Ic209 is substantially equal to the first subcurrent Ix. Since the first substream Jj is proportional to T0'5, the following applies:

Ic209 = c * T05 (9) 15 in which c represents a proportional constant and T is the absolute temperature.

The saturation current of the second bipolar junction transistor 209, IS209 can be represented as: IS209 = b * T2'5 e "Eg / kT (10) wherein b represents a proportional constant and Eg is the bandwidth energy of silicon, or 1, 12 eV.

From equations (9) and (10) it can be deduced that: B v τ, J v T. C209 - J. in C209 30 V τ BI cat. - V τ 1 ^ - 05 V r / 2

Ia09 BT cT03, 2C1 "T

d V T. r __Hr, r (11-14) 35 β τ ln 1 sm ~ T m 1 5209 _YLt B I saoB 5 Fr. E g, r 2J5 V T E Jq

In cooperation with 9T - 2 r fer2 Vt - r ~ - 18 -

Substituting equations (11) - (14) in equation (8) provides the temperature coefficient of the base-emitter voltage 5 of the second bipolar junction transistor 209, or the temperature coefficient of V ^: VT, r, VT / 2 VT 2 SV TE , / q

Qj. - rj. in l cxf) ψ ψ ~ in i saa ψ j · 10 Vm ~ 2 Vt-EJq

T

In one example, the base-emitter voltage of the second bipolar junction transistor Vbei = 0.8 V, the thermal voltage VT = 15 is 26 mV, the parameter Eg / q = 1.12 V, and the absolute operating temperature t = 300 K. In In this case, the obtained temperature coefficient of the base-emitter voltage of the second bipolar junction transistor is -1.2 mV / C.

Back to equation (7), the temperature coefficient of the first term of the equation is -1.2 mV / C> the temperature coefficient of the second term of the equation is -2.5 mV / C and the temperature coefficient of the third term of the comparison is 0.4 mV / C. The mentioned coefficients are characteristic values and can change from process to process.

In view of the above, it can be determined that the gate voltage of the fourth NMOS transistor 201,. is inversely proportional to the temperature, and in particular in the industrial operating range from -55 ° C to 125 ° C, Vgn is reduced proportionally, in other words, Vgn decreases with increasing temperature.

Although the third term of the equation (7) increases with temperature, for typical values of m and n (e.g. m - 7 and n = 2), the slope of this term is 0.4 mV / C. Therefore, as the temperature rises, the combined drop of the first two terms dominates the rise of the third term in equation (7). Thus, the net effect is that the gate voltage of the fourth NMOS transistor Vg220 drops approximately linearly with increasing temperature in the temperature range of interest. Therefore, the PTAT current generator - 19 - 200 generates both the first subcurrent Ii and a voltage Vga, which decreases with temperature. This voltage Vgn is used to generate the IPTAT current, as described below. Since no integrated resistors are used in the PTAT generator 200, the generated first sub-current I1 is not sensitive to process variations.

The IPTAT current generator 400 includes a control voltage source 410 and a second sub-current generator 412.

The control voltage source 410 comprises a fifth PMOS transistor 401 and a sixth PMOS transistor 402 which are connected in series between the first reference voltage VDD and a fifth node 414.

The gate of the fifth PMOS transistor is coupled to the first node 240 and the gate of the sixth PMOS transistor is coupled to the first bias voltage Vcasp. The control voltage source 410 further comprises a fifth NMOS transistor 403 and a sixth NMOS

transistor 404 coupled in series between the fifth node 414 and the second reference voltage GND. The gates of the fifth NMOS transistor 403 and the sixth NMOS transistor 404 are coupled to their sources, so that the fifth and sixth NMOS transistors 403, 404 diode-20 are connected and therefore act as diodes.

The second subcurrent generator 412 of the IPTAT current generator 400 comprises a seventh PMOS transistor 407 connected in series between the first reference voltage VDD and a sixth node 416. The gate of the seventh PMOS transistor 407 is coupled to the sixth node 416. The second sub-current generator 412 of the IPTAT

current generator 400 further comprises a seventh NMOS transistor 405 and an eighth NMOS transistor 406 connected in series between the sixth node 416 and the second reference voltage GND. The gate of the seventh NMOS transistor 405 is coupled to the second node 242 at the gate of the fourth NMOS transistor Vgn201, and the gate of the eighth NMOS transistor 406 is coupled to the fifth node 414.

The control voltage source 410 operates to ensure that the voltage supplied from the fifth node 414 to the gate 35 of the eighth NMOS transistor 406, Vg406, causes the eighth NMOS transistor to operate in the linear region. By ensuring the operation of the eighth NMOS transistor 406 in the linear region, the eighth NMOS transistor operates in the same manner as a resistor.

- 20 -

As described above, the voltage on the gate of the fourth NMOS transistor Vg '201 is inversely proportional to the operating temperature. Since this voltage is applied to the gate of the seventh NMOS transistor 405, the second subcurrent I2 is generated inversely proportional to the operating temperature.

The drain current l2 of the eighth NMOS transistor 406 can be represented as: 12 = ~ T7 --- · V (16) # / n405 + r ώ406 * "Γ £ ^ 406 where ga405 is the transconductance of the seventh NMOS transistor 405 Vga is the gate voltage Vg406 of the eighth NMOS transistor 406, and r <to «06 is the drain source resistor of the eighth NMOS transistor 406. The approximation of equation (16) is true as r ^ to» 1 / 9m * osi which can be achieved by providing the eighth NMOS transistor 406 with a relatively small dimension ratio (W / L ratio).

The resistance of the eighth NMOS transistor 406, ^ 406, can be expressed as: 20 r__1_ *** (W / L) m (V ^, - V ») (17)

The gate voltage of the NMOS transistor 406, V7ioff, can be represented as: 25 ^ Γ * 40β = V £ S404 + V £ 3406 -J 21 PW, y J 2ip «3 V P, C. (W)« V P.C. (R7L) e 30 V 2htW / L) m / (W / L) m V 2Ix {W / L) J {W / L) mp, C «(W / i)« + P „C“ {W / L ) <b + 2V * 2 (W / L) μ C «WL) an (g ^ m) ¥ P„ (W / Z,) ** 2 (^ en) 2 35, (W / L) tm / fcT v2 +. 2 (m) M P.Cm) a (-7 µm)

P 'C. (WX) «2 (^ - 1) * A

=. _In_m_ / J _ (WO (W / D ^ T ../ (W / L) 401 (W / L) and X Λ Q Vn-1 \ V (W / L) axis (W / L) *, V OF / Oe (m) «T2 V * 40 (18) - 21 - where m = IS2i / Is209 and where n - (W / L) 20i / (W / L) 202, from equation (6) above, and where the body effect of the fifth NMOS 5 transistor is considered negligible.

Now substituting equation (18) in equation (17) provides another expression for the resistance of the eighth NMOS transistor 406, Titos-rds406 10 "'nv / L) f kT fnmfj lW / L) m (W / L) m J (m) «~ 1 (19) μ» C “(m)« li TlS-11V (W / L) m (W / L) „1 (W / L) Z (W / L) ZI * \

In this representation it can be seen that the first term between the square brackets in the denominator is proportional to the temperature and the second term between the square brackets in the denominator, or inversely proportional to the temperature, which is a known property of MOSFET- establishments. In this way the effective resistance of the eighth NMOS transistor 406, r ^ os is made independent of the temperature, the resistance value r ^ os is controlled solely according to the dimension ratio (W / L), or the ratio of channel width W to of channel length L, of the fifth PMOS transistor 401, the fifth NMOS transistor 403, the sixth NMOS transistor 404 and the eighth NMOS transistor 406, the fourth NMOS transistor 201 and the first PMOS transistor 208. By controlling the dimension ratios, the eighth NMOS transistor can be forced to act as a resistor while not being subject to temperature dependence. Therefore, the IPTAT 400 containing the eighth NMOS transistor 406 can be forced to generate a second subcurrent I2 that is inversely proportional to the temperature, since the gate voltage of the eighth NMOS transistor 406, Vg406r is inversely proportional to the temperature, while that is not subjected to temperature dependent operation. It is assumed that the effect of: 'in equation (19) is not taken into account. Considering this effect: "V „1.5 as mentioned above, and r ^ oe increases with temperature. Back to equation (16), if the temperature rises, the numerator (Vgn) decreases, while the denominator rises. Therefore, in this way, the second substream I2 decreases with temperature. Resistors - 22 - are very sensitive to process variation and also temperature dependent. Therefore, by eliminating resistors in the present configuration, sensitivity to process variation and temperature dependence are largely reduced.

During use, the first bias voltage VcaSp and the second bias voltage Vcasn ensure that the PMOS transistors 205, 206 and 402 and the NMOS transistors 203, 204 operate in the saturation region, respectively. Additionally, in one embodiment, the respective size ratios of the first and third PMOS transistors 208, 207, the second and fourth NMOS transistors 206, 205, and the first and third PMOS transistors 204, 203 are the same. This is because Ii = Ij 'in the PTAT power generation circuit 200.

The transistors with different dimension ratios are the fourth and second NMOS transistors 201, 202 and the second and first bipolar junction transistors 209, 210. This ensures that m and n of equation (6) are not equal to 1. If m and η 1 equation (6) no longer applies.

The adder circuit 500 includes a first adder circuit current mirror 520, a second adder circuit current mirror 530 and a third adder circuit current mirror 540.

The first addition circuit current mirror 520 comprises an eighth PMOS transistor 508 and a ninth PMOS transistor 509 which are connected in series between the first reference voltage VDD and a seventh node 514. The gate of the eighth PMOS transistor 508 is

coupled to the first node 240 and the port of the ninth PMOS

transistor 509 is coupled to the first bias voltage Vcasp. The first addition current mirror 520 provides a mirrored current of the first sub stream IJ to the seventh node 514.

The second addition circuit current mirror 510 comprises a tenth PMOS transistor 510 which is coupled between the first reference voltage VDD and the seventh node 514. The gate of the tenth PMOS transistor 510 is coupled to the sixth node 416.

The second sum current mirror 530 provides a mirrored current from the second sub-current I2 to the seventh node 514.

At the seventh node, the mirrored currents of the first and second substromes I1, I2 are combined or added to provide a sum stream I3. The sum current I3 is supplied as the third adder circuit current mirror 540, which comprises a ninth NMOS trans-40 sistor 511 which is coupled between the seventh node 514 and - 23 - sistor 511 which is coupled between the seventh node 514 and the second reference voltage gnd, and a tenth NMOS transistor 512 coupled between a set node 516 and the second reference voltage GND. The gates of the ninth and tenth NMOS 5 transistors 511, 512 are coupled to each other and to the seventh node. The sum current I3 flows through the ninth NMOS transistor 511 and is mirrored at the tenth NMOS transistor 512, which draws the resulting bias current Ibia3 from a circuit connected to the bias node 516.

As mentioned above, the mirrored current of the first substroom I2 is proportional to the temperature, while the mirrored current of the second substream I2 is inversely proportional to the temperature. Therefore, the summed bias current I3, which is a mirrored current of the sum current I3, can be represented as: r (WOm. IW / Dη, 1 (W / L) w (20) '' '(W / L) w II WD w '(W / L) ai

Therefore, by controlling the respective dimension ratios of the transistors 208, 407, 508, 510, 511 and 512, the bias current Ibias can be kept at a constant value which is completely dependent on the dimension ratios of the transistors and is independent of the temperature. and process variation. The first sub stream J 1 and the second sub stream 12 must be weighted ((W / L) 530 / (W / L) 200 and (W / L) S10 / (W / L) 407, before they are added so that the addition is constant with respect to temperature, and this addition must be strengthened or weakened before it is applied, for example according to ((W / L) 512 / (W / L) 5n) since different applications require different bias currents.

30 Comparison (20) ensures this.

FIG. 2 is a circuit diagram of a second embodiment of a bias current generating circuit in accordance with the present invention. Referring to FIG. -2, the bias current generating circuit comprises a proportional-to-absolute-temperature 35 (PTAT) -current generator 200, an inversely-proportional-to-absolute-temperature (IPTAT) -current generator 400, and an adder circuit 500, as described above, and further comprises a bias voltage generator 300 and a startup circuit 100.

The bias voltage generator 320 generates the first bias voltage Vcasp which is supplied to the PMOS cascade current mirror 210 of the PTAT current generator 200. The second bias voltage generator 330 generates the second bias voltage Vcasn which is supplied to the NMOS cascade current mirror 220 of the PTAT current generator 200.

The first bias voltage generator 320 includes an eleventh PMOS transistor 307 and an eleventh NMOS transistor 308 connected in series between the first reference voltage VDD and the second reference voltage GND. Additionally, a twelfth PMOS transistor 311 and a twelfth NMOS transistor 309 are connected in series between the first reference voltage VDD and the second reference voltage GND. Also, the thirteenth and fourteenth PMOS transistors 312, 313 and a thirteenth NMOS transistor 310 are coupled in series between the first reference voltage VDD and the second reference voltage GND. The gate 15 of the eleventh PMOS transistor 307 is coupled to the first node 240. The gate of the eleventh NMOS transistor 308 is coupled to a connection between the eleventh PMOS transistor 307 and the eleventh NMOS transistor 308, and is coupled to the gates of the twelfth and thirteenth NMOS transistors 309, 310. The gate of the twelfth PMOS transistor 311 is coupled to a connection between the twelfth PMOS transistor 311 and the twelfth NMOS transistor 309, and is coupled to the gate of the thirteenth PMOS transistor 312 The gate of the fourteenth PMOS transistor 313 is coupled to a connection between the fourteenth PMOS transistor 313 and the thirteenth NMOS transistor 310 and provides the first bias voltage Vcasp to the start-up circuit 100, the PTAT power generator 200 and the IPTAT power generator 400.

The second bias voltage generator 330 includes a fifteenth PMOS transistor 301 and a fifteenth NMOS transistor 305 connected in series between the first reference voltage VDD and an eighth node 518. In addition, a sixteenth PMOS transistor 302, a fourteenth NMOS transistor 303 and a sixteenth NMOS transistor 304 coupled in series between the first reference voltage VDD and the eighth node 518. A third PNP-type bipolar junction transistor 306 is coupled in a diode configuration between the eighth node and the second reference voltage GND. The gates of the fifteenth and

sixteenth PMOS transistors 301, 302 are coupled to the first node 240. The gate of the fifteenth NMOS transistor 305 is coupled to a connection between the fifteenth PMOS transistor 301 and the fifteenth NMOS transistor 305, and is coupled to a port 40 of the sixteenth NMOS transistor 304. The gate of the fourteenth NMOS

Transistor 303 is coupled to a connection between the sixteenth PMOS transistor 302 and the fourteenth NMOS transistor 303, and provides the second bias voltage Vcas "to the PTAT current generator 200 and the start-up circuit 100. The basis of the third bipolar junction transistor 306 is coupled to the second reference voltage GND.

The second bias voltage Vcasn can be determined as follows:

Vcasn ~ Vbe3 t ^ ds304 t Vgs303 (21) 10 wherein ν &> 3 is the base-emitter voltage of the third bipolar junction transistor 306, the drain-source voltage drop across the sixteenth NMOS transistor 304 and Vgs303 the gate-source voltage. on the fourteenth NMOS transistor is 303.

In order to generate a suitable voltage for V ^ 3, the combination of the currents flowing through the fifteenth and sixteenth PMOS transistors 301 and 302 must, in combination, be p times as large as the current flowing through the transistor 207 where p represents the dimension ratio of the third bipolar junction transistor 306 relative to that of the first bipolar junction transistor 209. It is common for p to be selected as 1, therefore:

In the light of equation (22), in order to generate a suitable voltage for l ^ 304, care must be taken that: 30 (TL + m », and (W / L) 3oa (W / L) ane> (24 35 (W / L) 305 "(W / L) 301

To generate a suitable voltage for Vgs303, it must be ensured that: - 26 - (W / L) m (W / L) 304 iW / L) m <25) (m) ^ (m) 2oi ( rjan

The first bias voltage can be determined as follows: 5 V ^ VDD * Vds3i2 + (26) wherein the drain source voltage of the thirteenth PMOS transistor is 312 and has a negative value, and V9a313 is the gate source voltage of the fourteenth PMOS transistor 313 , and has a negative value.

To ensure a suitable value for Vd3312 and Vga313, the dimensions of the transistors must be chosen such that: 15 (W / Dm (W / Dmn (White) M2 (W / L) a «(27) (W! T ) m '(W / l) m' W / Osu (W / L) m and 20 <m) illD (W / L) 312 (28) (WD «e (HW.) au to ensure that the second, fourth and sixth PMOS transistors 206, 205, 402 operate in the saturation region.

The bias voltage generator 300 of FIG. 2 is an exemplary embodiment of a voltage generator for generating the first and second bias voltages. Other embodiments for generating the first and second bias voltages are equally applicable to the principles of the present invention.

The boot circuit 100 of FIG. 2 ensures that the PTAT power generator can overcome a degenerate setting upon system boot. The degeneration setting refers to a state in which a transistor cannot conduct current even when the transistor is in an on state.

The boot circuit 100 includes seventeenth and eighteenth PMOS transistors 101, 102 and nineteenth and twentieth NMOS transistors 105, 106 which are connected in series between the first reference voltage VDD and the second reference voltage GND. A 40 seventeenth NMOS transistor 103 is coupled between the first 27 node 240 and the second reference voltage GND. An eighteenth NMOS transistor 104 is coupled between the first bias voltage Vcasp and the second reference voltage GND. Gates of seventeenth and eighteenth PMOS transistors 101, 102 are coupled to the second reference voltage GND. Gates of the seventeenth and eighteenth NMOS transistors 103, 104 are coupled to a connection between the sixteenth PMOS transistor 102 and the nineteenth NMOS transistor 105. A gate of the nineteenth NMOS transistor 105 is coupled to the second bias voltage Vcasn. A gate of the twentieth NMOS transistor 106 is coupled to the second node 242.

When power is supplied to the system, if the transistors 204 and 202 do not carry any current, then the transistors 105 and 106 also do not carry any current. It follows that no current flows through transistors 101 and 102. Therefore, the voltage at the drain node of transistor 105, namely Vst, must be high, which turns on 103 and 104. In this case, in the start-up circuit, the voltages at the second node Vgp and the second bias voltage Vcasn become low voltages. This in turn causes the activation of the first and second PMOS transistors 208, 206, and current is injected into the first and second NMOS transistors 204, 202. This in turn increases the voltage levels of the second node Vgp and the second bias voltage Vcasn · As a result, transistors 201, 202, 203 and 204 are turned on, and transistors 105 and 106 are turned on similarly. A relatively small dimension ratio (W / L) (1 pm / 20 μ111) ratio is selected for transistors 101 and 102, so that when transistors 101 and 102 are turned on, the voltage Vst is much lower than the threshold voltage. Thereafter, when the current flows through NMOS transistors 201, 202, 203 and 204, NMOS transistors 103 and 104 are turned off, which has no effect on the normal operation of the circuit. In this way, the circuit is successfully started during power-up in a manner that overcomes degenerate setting.

FIG. 3 is a circuit diagram of a third embodiment of a bias current generating circuit in accordance with the present invention. Like the second embodiment described above, the bias current generating circuit of the third embodiment comprises a startup circuit 100A, a PTAT current generator 200A, a bias voltage generator 300A, an IPTAT current generator 400A 40 and an adder circuit 500A.

- 28 -

In the third embodiment, the purpose and operation of the start-up circuit 100A, the PTAT power generator 200A, the bias voltage generator 300A, the IPTAT power generator 4Ö0A and the adder circuit 500A are substantially the same as the equivalent circuits of the first embodiment and the second embodiment of FIG. 1 and 2. However, in the adder circuit 100A, PMOS transistors 103A, 104A are used instead of the seventeenth and eighteenth NMOS transistors 103, 104. In the PTAT current generator 200A, NPN-type bipolar junction transistors 210A, 209Ά are in series placed between the first reference voltage VDD and the PMOS cascade current mirror. In the second bias voltage generator 300A, NPN type bipolar junction transistors 306A, PMOS transistors 303A, 304A, 305A and NMOS transistors 301A, 302A are used. In the first bias voltage generator 320A, PMOS transistors 309A, 310A and NMOS transistors 307A, 308A, 311A, 312A and 313A are used. In the IPTAT power generator 400A, PMOS transistors 403A, 404A, 405A, 406A and NMOS transistors 401A, 402A are used. In the adder circuit 500A, the first adder circuit current mirror 520A includes NMOS transistors 508A, 509A, the second adder circuit current mirror 530A includes NMOS transistor 510A, and the third adder circuit current mirror 540A includes PMOS transistors 51A, 512A.

In this manner, like the first and second embodiments above, the third embodiment of the present invention generates a bias current Ibias which is a combination of a first substroom I1 proportional to a rising temperature, and a second substroom I2 which inversely proportional to rising temperature in a manner that moderates or induces the effects of temperature and process variation.

Although this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be apparent to those skilled in the art that various variations in form and detail may be made herein without departing from the scope of the invention as defined in the appended claims.

1 ft 7 n l λ 1

Claims (46)

A bias current generator comprising: a proportional-to-the-absolute-temperature (PTAT) current generator that comprises only active circuit elements and which comprises a. generates first current that is proportional to the operating temperature; 5 a reverse-proportional-to-the-absolute-temperature (IPTAT) current generator which comprises only active circuit elements and which generates a second current which is inversely proportional to the operating temperature; and an adder circuit that adds the first and second currents 10 to generate a bias current. The bias current generator according to claim 1, wherein the bias current is generated substantially independently of the operating temperature. 15 The bias current generator according to claim 1, wherein the PTAT power generator comprises: a PMOS cascode current mirror comprising: a first PMOS transistor and a second PMOS transistor 20 connected in series between a first reference voltage and a first node, a gate of the first PMOS transistor is coupled to the first node and a gate of the second PMOS transistor is coupled to a first bias voltage; and a third PMOS transistor and a fourth PMOS transistor connected in series between the first reference voltage and a second node, a gate of the third PMOS transistor being coupled to the first node and a gate of the fourth PMOS transistor being coupled to the first bias voltage; an NMOS cascade current mirror comprising: a first NMOS transistor and a second NMOS transistor connected in series between the first node and a third node, a gate of the first NMOS transistor being coupled to a second bias voltage and a gate of the second NMOS transistor is coupled to the second node; and a third NMOS transistor and a fourth NMOS transistor connected in series between the second node and a fourth node, a gate of the third NMOS transistor being coupled to the second bias voltage and a gate of the third fourth NMOS transistor is coupled to the second node; and a first diode connected in series between the third node and a second reference voltage; and a second diode connected in series between the fourth node and the second reference voltage. 4. The bias current generator according to claim 3, wherein the first reference voltage comprises a supply source voltage and wherein the second reference voltage comprises a ground voltage. The bias current generator according to claim 3, wherein the first diode comprises a PNP-type bipolar junction transistor, an emitter of which is connected to the third node and of which a base and. The collector is connected to the second reference voltage and the second diode comprises a PNP-type bipolar junction transistor, an emitter of which is connected to the fourth node and of which a base and collector are connected to the second reference voltage. 20 6. The bias current generator according to claim 3, wherein the first bias voltage is at a voltage level sufficient to saturate the second and fourth PMOS transistors, and wherein the second bias voltage is at a voltage level sufficient to saturate the first and third NMOS transistors . The bias current generator according to claim 3, wherein the IPTAT power generator comprises: a fifth PMOS transistor and a sixth PMOS transistor connected in series between the first reference voltage and a fifth node, a gate of the fifth PMOS transistor being coupled to the first node and a gate of the sixth PMOS transistor is coupled to the first bias voltage; and a fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the second reference voltage, wherein the fifth and sixth NMOS transistors are each configured in a diode configuration; a seventh PMOS transistor connected between the first reference voltage and a sixth node, the gate of the 40 seventh PMOS transistor being coupled to the sixth node; and - a seventh NMOS transistor and an eighth NMOS transistor connected in series between the sixth node and the second reference voltage, a gate of the seventh NMOS transistor being coupled to the second node, and a gate of the fifth eighth NMOS transistor is coupled to the fifth node. The bias current generator according to claim 7, wherein the adding circuit comprises: an eighth PMOS transistor and a ninth PMOS transistor connected in series between the first reference voltage and a seventh node, a gate of the eighth PMOS transistor being coupled to the first node and wherein a gate of the ninth PMOS transistor is coupled to the first bias voltage; a tenth PMOS transistor connected between the first reference voltage and the seventh node, a gate of the tenth PMOS transistor being coupled to the sixth node; a ninth NMOS transistor connected between the seventh node and the second reference voltage, the ninth NMOS transistor's gate being coupled to the seventh node; and a tenth NMOS transistor connected between a set node at which the set current is drawn and the second reference voltage, the gate of the tenth NMOS transistor being coupled to the seventh node. The bias current generator of claim 3, further comprising a bias voltage generator that includes a first bias voltage generator that generates a first bias voltage and a second bias voltage generator that generates a second bias voltage, the first bias voltage generator comprising: an eleventh PMOS transistor and an eleventh NMOS transistor series is between the first reference voltage and the second reference voltage, the gate of the eleventh PMOS transistor being coupled to the first node, the gate of the eleventh NMOS transistor being coupled to a connection between the eleventh PMOS transistor and the eleventh NMOS transistor ; a twelfth PMOS transistor and a twelfth NMOS transistor that are in series between the first reference voltage and the second reference voltage, the gate of the twelfth PMOS transistor being coupled to a connection between the twelfth PMOS transistor and. The twelfth NMOS transistor, the gate of the twelfth NMOS transistor being coupled to the gate of the eleventh NMOS transistor; and a thirteenth PMOS transistor, a fourteenth PMOS transistor and a thirteenth NMOS transistor that are in series between the first reference voltage and the second reference voltage, the gate of the thirteenth PMOS transistor being coupled to the gate of the twelfth PMOS transistor, the gate of the fourteenth PMOS transistor is coupled to a connection between the fourteenth PMOS transistor and the thirteenth NMOS transistor, the gate of the thirteenth NMOS transistor being coupled to the gate of the twelfth NMOS transistor, the connection of the fourteenth PMOS transistor and the thirteenth NMOS transistor provides the first bias voltage; and wherein the second bias voltage generator comprises: a fifteenth PMOS transistor and a fifteenth NMOS transistor in series between the first reference voltage and an eighth node, the gate of the fifteenth PMOS transistor being coupled to the first node, the gate of the fifteenth NMOS transistor is coupled to a connection between the 15th PMOS transistor and the 15th NMOS transistor; a sixteenth PMOS transistor, a fourteenth NMOS transistor and a sixteenth NMOS transistor that are in series between the first reference voltage and the eighth node, the gate of the sixteenth PMOS transistor being coupled to the first node, the gate of the fourteenth NMOS transistor is coupled to a connection between the sixteenth PMOS transistor and the fourteenth NMOS transistor, the gate of the sixteenth NMOS transistor being coupled to the gate of the fifteenth NMOS transistor; and a third diode connected in series between the eighth node and the second reference voltage, the connection of the sixteenth PMOS transistor and the fourteenth NMOS transistor providing the second bias voltage. 10. The bias current generator according to claim 9, wherein the third diode comprises a PNP-type bipolar junction transistor, an emitter of which is connected to the eighth node and a base and collector are connected to the second reference voltage. - 33 - The bias current generator according to claim 3, further comprising a startup circuit that ensures that the transistors in the PTAT current generator and the IPTAT current generator initialize beyond a degenerate setting. 5 12. The bias current generator according to claim 11, wherein the start-up circuit comprises: a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth NMOS transistor and a twentieth NMOS transistor connected in series between the first reference voltage and the second reference voltage, seventeenth and eighteenth PMOS transistors are each coupled to the second reference voltage, one gate of the nineteenth NMOS transistor being coupled to the second bias voltage and a gate 15 of the twentieth NMOS transistor being coupled to the second node; a seventeenth NMOS transistor connected in series between the first node and the second reference voltage; and an eighteenth NMOS transistor connected in series between the first bias voltage and the second reference voltage. The bias current generator according to claim 1, wherein the adder circuit comprises: a first current mirror that generates a first mirrored current in response to the first current generated by the PTAT; a second current mirror that generates a second mirrored current in response to a second current generated by the PTAT; and a third current mirror that generates a bias current based on the sum of the first mirrored current and the second mirrored current. The bias current generator according to claim 1, wherein the first current is further generated as a function of a first dimension ratio of at least one transistor along a first one. current path to a second dimension ratio of at least one transistor along a second current path, wherein the second current path and the first current path are in a current mirror configuration, the first and second dimension ratios for corresponding transistors in the first and second current paths being different to be. 15. The bias current generator according to claim 14, wherein the second current is further generated as a function of a voltage generated in the PTAT current generator that is shared by an active circuit element in the IPTAT current generator to generate a second current. The bias current generator according to claim 1, wherein the PTAT current generator comprises: a first current path comprising a plurality of transistors; and a second current path comprising a number of transistors, wherein at least one of the number of transistors of the second current path corresponds to one of the number of transistors of the first current path, wherein at least one pair of the corresponding transistors of the first and second current paths has a different size ratio, the first current being generated in response to the different size ratio of the corresponding transistors of the first and second current paths. 17. The bias current generator according to claim 16, wherein the IPTAT current generator comprises a third current path with a number of transistors, the second current being further generated as a function of a voltage generated in the PTAT current generator that is shared by a transistor in the third flow path to generate the second flow. The bias current generator according to claim 1, wherein the PTAT power generator comprises: a first diode connected in series between a first reference voltage and a third node; a second diode connected in series between the first reference voltage and a fourth node; 35 a PMOS cascode current mirror comprising: a first PMOS transistor and a second PMOS transistor connected in series between the third node and a first node, and a third PMOS transistor and a fourth PMOS transistor connected in series between the fourth node and a second node, wherein ports of the first and third PMOS transistors are coupled to the second node, and ports of the second and fourth PMOS transistors are coupled to a first bias voltage; 5 and an NMOS cascade current mirror comprising: a first NMOS transistor and a second NMOS transistor connected in series between the first node and a second reference voltage, and a third NMOS transistor and a fourth NMOS transistor connected in series between the second node and the second reference voltage, with gates of the first and third NMOS transistors coupled to a second bias voltage, and gates of the second and fourth NMOS transistors coupled to the first node. The bias current generator according to claim 18, wherein the first reference voltage comprises a power supply voltage and the second reference voltage comprises a ground voltage. 20 20. A bias current generator according to claim 18, wherein the first diode comprises an NPN-type bipolar junction transistor, an emitter of which is connected to the third node and of which a base and collector are connected to the first reference voltage and wherein the second diode is an NPN-type bipolar junction transistor, an emitter of which is connected to the fourth node and a base and collector of which are connected to the first reference voltage. The bias current generator of claim 18, wherein the first bias voltage is at a voltage level sufficient to saturate the second and fourth PMOS transistors, and wherein the second bias voltage is at a voltage level sufficient to saturate the first and third NMOS transistors. The bias current generator according to claim 18, wherein the IPTAT current generator comprises: a fifth PMOS transistor and a sixth PMOS transistor connected in series between the first reference voltage and a fifth node, the fifth and sixth PMOS transistors each being 40 configured in a diode configuration; and - a fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the second reference voltage, a gate of the fifth NMOS transistor being coupled to the second bias voltage and a gate of the sixth NMOS 5 tran -sistor is coupled to the first node; a seventh PMOS transistor and an eighth PMOS transistor connected in series between the first reference voltage and a sixth node, with a gate of the seventh PMOS transistor coupled to the fifth node, and a gate of the eighth PMOS transistor coupled to the second node; and a seventh NMOS transistor connected between the sixth node and the second reference voltage, the gate of the seventh NMOS transistor being coupled to the sixth node. The bias current generator according to claim 22, wherein the adder circuit comprises: an eighth NMOS transistor and a ninth NMOS transistor connected in series between a seventh node and the second reference voltage, a gate of the eighth NMOS transistor 20 being coupled to the second bias voltage and a gate of the ninth NMOS transistor is coupled to the first node; a tenth NMOS transistor connected between the seventh node and the second reference voltage, a gate of the tenth NMOS transistor coupled to the sixth node; A ninth PMOS transistor connected between the first reference voltage and the seventh node, the gate of the ninth PMOS transistor being coupled to the seventh node; and a tenth PMOS transistor connected between the first reference voltage and a bias node on which the bias current 30 is drawn, the gate of the tenth NMOS transistor being coupled to the seventh node. A bias current generator comprising: a proportional to the absolute temperature (PTAT) current generator 35 which generates a first current that is proportional to the operating temperature; comprising: a first current path comprising a plurality of transistors; and a second current path comprising a number of transistors, wherein at least one of the number of transistors of the second current path corresponds to one of the number of 40 transistors of the first current path, wherein at least one pair of corresponding transistors of the first and second current paths have a different dimension ratio, the first current being generated in response to the different dimension ratio of the corresponding transistors of the first and second current paths; 5 an inversely-proportional-to-the-absolute-temperature (IPTAT) generator that generates a second current that is inversely proportional to the operating temperature, comprising: a third current path comprising a plurality of transistors, the second current being generated as a function of a voltage generated in the PTAT current generator 10 shared by a transistor in the third current path for generating the second current; and an adder circuit that adds the first and second currents to generate a bias current. The bias current generator according to claim 24, wherein the PTAT power generator comprises only active circuit elements. The bias current generator according to claim 24, wherein the IPTAT current generator comprises only active circuit elements. The bias current generator according to claim 24, wherein the bias current is generated substantially independently of the operating temperature. A bias current generator according to claim 24, wherein the PTAT power generator comprises: a PMOS cascode current mirror comprising: a first PMOS transistor and a second PMOS transistor connected in series between a first reference voltage and a first node, a gate of the first PMOS transistor 30 is coupled to the first node and a gate of the second PMOS transistor is coupled to a first bias voltage; and a third PMOS transistor and a fourth PMOS transistor connected in series between the first reference voltage and a second node, a gate of a third PMOS transistor 35 coupled to the first node and a gate of the fourth PMOS transistor coupled to the first bias voltage; an NMOS cascade current mirror comprising: a first NMOS transistor and a second NMOS transistor connected in series between the first node and a third 40 node, a gate of the first NMOS transistor being coupled to the second bias voltage and a gate of the second NMOS transistor is coupled to the second node; and a third NMOS transistor and a fourth NMOS transistor connected in series between the second node and a fourth node, a gate of the third NMOS transistor being coupled to the second bias voltage and a gate of the fourth NMOS transistor being coupled to the second node; a first diode connected in series between the third node and a second reference voltage; and a second diode connected in series between the fourth node and the second reference voltage. 29. Setting current generator according to claim 28, wherein the first reference voltage comprises a power supply voltage and wherein the second reference voltage comprises a ground voltage. 30. The bias current generator according to claim 28, wherein the first diode comprises a PNP-type bipolar junction transistor, an emitter of which is connected to the third node and of which a base and collector are connected to the second reference voltage and wherein the second diode is a PNP-type bipolar junction transistor, an emitter of which is connected to the fourth node and a base and collector of which are connected to the second reference voltage. 25 31. The bias current generator of claim 28, wherein the first bias voltage is at a voltage level sufficient to saturate the second and fourth PMOS transistors, and wherein the second bias voltage is at a voltage level sufficient to saturate the first and third NMOS transistors . The bias current generator according to claim 28, wherein the IPTAT current generator comprises: a fifth PMOS transistor and a sixth PMOS transistor connected in series between the first reference voltage and a fifth node, a gate of the fifth PMOS transistor being coupled to the first node and a gate of the sixth PMOS transistor is coupled to the first bias voltage; and a fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the second reference voltage, the fifth and sixth NMOS transistors each being configured in a diode configuration; a seventh PMOS transistor connected between the first reference voltage and a sixth node, the gate of the seventh PMOS transistor being coupled to a sixth node, and a seventh NMOS transistor and an eighth NMOS transistor connected in series between the sixth node and the second reference voltage, wherein a gate of the seventh NMOS transistor is coupled to the second node, and a gate of the eighth NMOS transistor is coupled to the fifth node. The bias current generator according to claim 32, wherein the adder circuit comprises: an eighth PMOS transistor and a ninth PMOS transistor connected in series between the first reference voltage and a seventh node, a gate of the eighth PMOS transistor being coupled to the first node and a gate of the ninth PMOS transistor is coupled to the first bias voltage; a tenth PMOS transistor connected between the first reference voltage and the seventh node, a gate of the tenth PMOS transistor being coupled to the sixth node; a ninth NMOS transistor connected between the seventh node and the second reference voltage, the ninth NMOS transistor gate being coupled to the seventh node; and a tenth NMOS transistor connected between a set node at which the set current is drawn and the second reference voltage, the gate of the tenth NMOS transistor being coupled to the seventh node. 30 The bias current generator according to claim 28, further comprising a bias voltage generator that comprises: a first bias voltage generator that generates the first bias voltage and a second bias voltage generator that generates the second bias voltage, the first bias voltage generator comprising: an eleventh PMOS transistor and an eleventh NMOS transistor in series between the first reference voltage and the second reference voltage, wherein the gate of the eleventh PMOS transistor is coupled to the first node, the gate of the eleventh - 40 - NMOS transistor being coupled to a connection between the eleventh PMOS transistor and the eleventh NMOS transistor; a twelfth PMOS transistor and a twelfth NMOS transistor in series between the first reference voltage and the second reference voltage, the gate of the twelfth PMOS transistor being coupled to a connection between the twelfth PMOS transistor and the twelfth NMOS transistor, the gate of the twelfth NMOS transistor is coupled to the port of the eleventh NMOS transistor; and a thirteenth PMOS transistor, a fourteenth PMOS transistor and a thirteenth NMOS transistor in series between the first reference voltage and the second reference voltage, the gate of the thirteenth PMOS transistor being coupled to the gate of the twelfth PMOS transistor, the gate of the fourteenth PMOS transistor is coupled to a connection between the fourteenth PMOS transistor and the thirteenth NMOS transistor, the gate of the thirteenth NMOS transistor being coupled to the gate of the twelfth NMOS transistor, the connection of the fourteenth PMOS transistor to the thirteenth NMOS transistor provides the first bias voltage; and wherein the second bias voltage generator comprises: a fifteenth PMOS transistor and a fifteenth NMOS transistor in series between the first reference voltage and an eighth node, the gate of the fifteenth PMOS transistor being coupled to the first node, the gate of the fifteenth NMOS transistor is coupled to a connection between the fifteenth PMOS transistor and the fifteenth NMOS transistor; a sixteenth PMOS transistor, a fourteenth NMOS transistor and a sixteenth NMOS transistor in series between the first reference voltage and the eighth node, the gate of the sixteenth PMOS transistor being coupled to the first node and the gate of the fourteenth NMOS transistor being coupled to a connection between the sixteenth PMOS transistor and the fourteenth NMOS transistor, the gate of the sixteenth NMOS transistor being coupled to the gate of the fifteenth NMOS transistor; and a third diode connected in series between the eighth node and the second reference voltage, the connection of the sixteenth PMOS transistor and the fourteenth NMOS transistor providing the second bias voltage. - 41 - The bias current generator according to claim 34, wherein the third diode comprises a PNP-type bipolar junction transistor, an emitter of which is connected to the eighth node and of which a base and collector are connected to the second reference voltage. 5 The bias current generator according to claim 28, further comprising a startup circuit which ensures that the transistors in the ΡΤΔΤ current generator and the IPTAT current generator initialize beyond a degenerate setting. 10 The bias current generator according to claim 24, wherein the startup circuit comprises: a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth NMOS transistor and a twentieth NMOS transistor connected in series between the first reference voltage and the. second reference voltage, wherein gates of the seventeenth and eighteenth PMOS transistors are each coupled to the second reference voltage, wherein a gate of the nineteenth NMOS transistor is coupled to the second bias voltage and a gate 20 of the twentieth NMOS transistor is coupled to the second node; a seventeenth NMOS transistor connected in series between the first node and the second reference voltage; and an eighteenth NMOS transistor connected in series between the first bias voltage and the second reference voltage. The bias current generator according to claim 24, wherein the adder circuit comprises: a first current mirror that generates a first mirrored current 30 in response to the first current generated by the PTAT; a second current mirror that generates the second mirrored current in response to the second current generated by the PTAT; and a third current mirror that generates the bias current based on the sum of the first mirrored current and the second mirrored current. The bias current generator according to claim 24, wherein the PTAT current generator comprises: 40 a first current path comprising a plurality of transistors; and - a second current path comprising a number of transistors, wherein at least one of the number of transistors of the second current path corresponds to one of the number of transistors of the first current path, wherein at least one pair of the corresponding transistors of the first and second current paths has a different dimension ratio, the first current being generated in response to the different dimension ratio of the corresponding transistors of the first and second current paths. The bias current generator according to claim 39, wherein the IPTAT current generator comprises a third current path with a plurality of transistors, the second current being generated as a function of a voltage generated in the PTAT current generator that is shared by an active circuit element in the IPTAT current generator 15 to generate the second stream. The bias current generator according to claim 24, wherein the PTAT current generator comprises: a first diode connected in series between a first reference voltage and a third node; a second diode connected in series between the first reference voltage and a fourth node; a PMOS cascade current mirror comprising: a first PMOS transistor and a second PMOS transistor connected in series between the third node and a first node, and a third PMOS transistor and a fourth PMOS transistor connected in series between the fourth node and a second node, wherein the gates of the first and third PMOS transistors 30 are coupled to the second node, and wherein gates of the second and fourth PMOS transistors are coupled to a first bias voltage; and an NMOS cascade current mirror comprising: a first NMOS transistor and a second NMOS transistor 35 connected in series between the first node and a second reference voltage, and a third NMOS transistor and a fourth NMOS transistor connected in series between the second node and the second reference voltage, wherein gates of the first and third NMOS 40 transistors are coupled to a second bias voltage, and wherein - 43 - gates of the second and fourth NMOS transistors are coupled to the first node. 42. Setting current generator according to claim 41, wherein the first reference voltage comprises a supply source voltage and wherein the second reference voltage comprises a ground voltage. The bias current generator according to claim 41, wherein the first diode comprises an NPN-type bipolar junction transistor, an emitter of which is connected to the third node and of which a base and collector are connected to the first reference voltage and wherein the second diode is an NPN-type bipolar junction transistor, an emitter of which is connected to the fourth node and a base and collector are connected to the first reference voltage. 44. Setting current generator according to claim 41, wherein the first bias voltage is at a voltage level sufficient to saturate the second and fourth PMOS transistors and wherein the second bias voltage is at a voltage level sufficient to saturate the first and third NMOS transistors. 45. The bias current generator according to claim 41, wherein the IPTAT current generator comprises: a fifth PMOS transistor and a sixth PMOS transistor connected in series between the first reference voltage and a fifth node, the fifth and sixth PMOS transistors each being configured in a diode configuration ; and a fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the second reference voltage, a gate of the fifth NMOS transistor being coupled to the second bias voltage and a gate of the sixth NMOS transistor being coupled to the first node; and a seventh PMOS transistor and an eighth PMOS transistor connected in series between the first reference voltage and a sixth node, a gate of the seventh PMOS transistor being coupled to the fifth node, and a gate of the eighth PMOS transistor coupled to the second node; and - a seventh NMOS transistor connected between the sixth node and the second reference voltage, the gate of the seventh NMOS transistor being coupled to the sixth node. The bias current generator according to claim 45, wherein the adder circuit comprises: an eighth NMOS transistor and a ninth NMOS transistor connected in series between a seventh node and the second reference voltage, a gate of the eighth NMOS transistor 10 being coupled to the second bias voltage and a gate of the ninth NMOS transistor is coupled to the first node; a tenth NMOS transistor connected between the seventh node and the second reference voltage, a gate of the tenth NMOS transistor being coupled to the sixth node; and a ninth PMOS transistor connected between the first reference voltage and the seventh node, the gate of the ninth PMOS transistor being coupled to the seventh node; and a tenth PMOS transistor connected between the first reference voltage and a bias node on which the bias current 20 is drawn, the gate of the tenth NMOS transistor being coupled to the seventh node. 1 0 30 43 1