LU504697B1

LU504697B1 - Thin film solar cell and corresponding production method

Info

Publication number: LU504697B1
Application number: LU504697A
Authority: LU
Inventors: Taowen Wang; Longfei Song
Original assignee: Univ Luxembourg; Luxembourg Inst Science & Tech List
Priority date: 2023-07-07
Filing date: 2023-07-07
Publication date: 2025-01-07
Also published as: WO2025012117A1

Abstract

The invention relates to thin film CIGS solar cells. A method for producing such solar cell comprises the steps of: providing a substrate (12); forming a back-electrode layer (14) on the substrate; forming a hole transport structure (20) on the back electrode layer, the hole transport structure comprising a hole transport layer (16) comprising p-type conductive material on the back-electrode layer and a stabilizing layer (18) on the hole transport layer, the stabilizing layer comprising a metal oxide and/or a metal nitride; and forming a semiconductor absorber layer (22) on the hole transport structure, the absorber layer comprising chalcogenide material. A corresponding thin film solar cell with such double-layer hole transport structure is also presented.

Description

1 | U504697

Thin film solar cell and corresponding production method

Technical field

The invention generally relates to the field of photovoltaic devices such as solar cells and solar panels, and more particularly to thin film solar cells and methods for producing same.

Background of the Invention

Solar cells are one class of energy source devices which harness a renewable source of energy in the form of light that is converted into useful electrical energy which may be used for numerous applications. Thin film solar cells are multi-layered semiconductor structures formed by depositing various thin layers and films of semiconductor and other materials on a substrate. These solar cells may be made into light-weight flexible sheets in some forms comprised of a plurality of individual electrically interconnected cells. The attributes of light weight and flexibility gives thin film solar cells broad potential applicability as an electric power source for use

In portable electronics, aerospace, and residential and commercial buildings where they can be incorporated into various architectural features such as roof shingles, facades, and skylights.

Thin film solar cells, such as CIGS (copper indium gallium selenide) solar cells, generally comprise a back contact or electrode formed on the substrate and a top contact or electrode formed above the back electrode and electrically connected thereto. In contrast to conventional Si solar cells, thin film solar cells generally have a fully metallic back contact (or back electrode layer), that causes the loss of light generated electrons by electron-hole recombination, also known as back surface recombination.

In order to improve the efficiency of the thin film solar cell, attempts have been made to limit this recombination.

Document US 2015/380596 A discloses a method for producing a thin film CIGS solar cell which mitigates the back surface recombination by a compositional gradient of Gallium that increases the conduction band edge energy towards the back contact. This gradient reduces backside recombination by keeping minority carriers away from the back contact, and can greatly reduce the non-radiative loss in open-circuit voltage. However, the band gap gradient leads to various losses: (i) the zone of the minimum band gap, which determines the absorption edge, is rather thin, which leads to non-absorption losses in the short circuit current; the gradual absorption onset leads to radiative losses in the open circuit voltage; and the regions with the highest content of Gallium near the back contact have been shown to exhibit an extremely low carrier lifetime below 100ps, which can be attributed to additional deep defects in high band gap chalcopyrite. Furthermore, from a technological point of view the need for a compositional gradient makes the absorber unnecessarily thick, which increases production cost.

Document CN 112786713 A discloses a method for producing a thin film CIGS solar cell which mitigates the back surface recombination by providing an additional layer between the back contact and the CIGS absorber layer. However, the additional layer is non-conductive and requires a structuration in order to transport holes, which complicates the production process and increases the production costs.

Object of the invention

Hence, there is a need for an improved design/manufacturing approach of thin film solar cells that does not present the above-mentioned drawbacks.

This object is achieved by a thin film solar cell according to claim 1.

General Description of the Invention

According to the present invention a method for producing a thin film solar cell comprises the steps of: providing a substrate; forming a back-electrode layer on the substrate layer; forming a hole transport structure on the back-electrode layer; forming a semiconductor absorber layer on said hole transport structure, the absorber layer comprising chalcogenide material,

3 | U504697 wherein the hole transport structure comprises a hole transport layer with p-type conductive material on the back-electrode layer and a stabilizing layer on the hole transport layer, the stabilizing layer comprising a metal oxide and/or a metal nitride.

The present invention relies on the use of a hole transport structure that comprises a hole transport layer, providing for the desired hole selectivity at the backside, combined with a stabilizing layer arranged as capping layer to block diffusion of the hole transport layer during manufacturing of the absorber layer (typically requiring heating of up to 590°C for CIS/CGIS material) and hence stabilize (or passivate) the latter. First tests have shown that such hole transport structure is thermally stable and compatible with the thin film manufacturing technologies. It provides a stable hole transport layer with good transport properties and demonstrates a passivation effect, comparable to the one of conventional Ga grading. Furthermore, performances in terms of lifetime of minority carriers and fill-factor demonstrate that the Ga grading is not essential to gain high-efficiency solar cells.

The avoidance of the conventional Ga grading structure simplifies the absorber deposition step since a homogeneous absorber layer may be formed. This reduces the absorber deposition process time and allows for thinner absorbers.

The layer stack thus obtained is ready to be processed according to conventional techniques to form the upper part of the solar cell. Hence the process typically includes the steps of — forming an electron transport layer above the absorber layer; and — forming a top electrode layer above the electron transport layer.

The present invention thus provides a process improvement to the field of thin film solar cells using on chalcogenide materials as absorbers.

Inthe present text, the expression “chalcogenide” material refers to a material of the group consisting of metallic sulfides, selenides and/or tellurides, i.e. to a material containing one or more chalcogen atoms (e.g. S, Se, or Te) bonded to one or more metal atoms, and having a crystallographic structure similar to one of the following materials:

— chalcopyrite, typically a compound according to formula (Agx, CU1-x)(INy, Gaz, Al4-y-z)(SEx, Si, Te1-k1)2, where O<x<1, 0sk+I<1, and Osy+z<1; — Kesterite, typically CuZnSn(Sk, Se1x); or — orthorhombic crystal: typically (Sbx Bi-x)2(Sy, S@1-y)3.

In the following, possible compositions for the various layers, as they are formed/deposited on the respective underlying layer, are described.

In embodiments, the hole transport layer comprises, or consists of, p-type chalcogenide material.

Exemplary chalcogenide materials for forming the hole transport layer include materials selected from the group consisting of Cu(In,Ga)Se2, Cu(In,Ga)(Se,S)2,

CulnSe2, CuGaSe2, CulnS2, Cu(In,Ga)S2, (Cux, Ag1-x)(Gay,Al1-y)(Sz, Se1-z)2, and their mixtures, in particular CuGaSe2 or CuAlSe2.

The hole transport layer may have a thickness between 10 and 200 nm, in particular between 50 and 100 nm.

The stabilizing layer, in turn, may comprise, or consist of, a stoichiometric or non- stoichiometric metal oxide and/or metal nitride. The terms oxides and nitrides should be understood as including one or several forms of oxides, respectively nitrides, for a given metal.

In practice, the stabilizing layer may be an oxide or nitride layer of a single metal.

The use of oxide/nitride of a single metal may be easier process-wise. However, the stabilizing layer may also comprise a mixture of oxides of different metals, a mixture of nitrides of different metals, or respectively a mixture of one or more metal oxides with one or more metal nitrides.

Preferred metals for the oxides, respectively nitrides, include metals and semi- metals, including namely but not limited to Si, Mo, Al, Ga, In, Ti, Hf.

Hence, the stabilizing layer may typically comprise, or consist of, compounds such as MNx, MOx and/or MNxOy, where M is selected from Si, MO, Al, Ga, In, Ti and

Hf, and x and y can be integers (stoichiometric compound) or decimal values (non- stoichiometric).

In particular embodiments, the stabilizing layer may be formed as a metal sesquioxide or a metal dioxide, or a mixture thereof. For example, the material for the stabilizing layer may be selected from the group comprising AI203, Ga203,

In203, TiO2, MoO2, and their mixtures.

Ina particular embodiment the hole transport structure is formed by depositing an

InOx layer over a CGSe layer.

The thickness of the stabilizing layer may be between 1 and 100 nm.

Preferably, a conduction band minimum (CBM) of the stabilizing layer is greater than the CBM of the absorber layer. There is thus an offset of the conduction band (CBM) between the stabilizing layer and the absorber layer, preferably of at least 0.3 eV.

In embodiments, the stabilizing layer is deposited in direct contact with the hole transport layer. Alternatively, an intermediate layer may be formed between the stabilizing layer and the hole transport layer, in particular a conductivity enhancing layer.

Conductivity of the hole transport structure may be improved by doping at least one the hole transport layer and the stabilizing layer. A suitable dopant is e.g. copper.

Accordingly, a copper layer can be formed/arranged adjacent the stabilizing layer.

In particular, the copper layer may be formed between the hole transport layer and the stabilizing layer.

Such copper layer may have a thickness similar to the stabilizing layer, i.e. of between 1 to 100 nm.

It may be noted that the high temperatures applied when depositing the absorber layer will typically cause migration/diffusion of copper, such that a thin copper layer may typically entirely disappear.

The fact that at least part of the copper atoms from the intermediate copper layer migrate to the stabilizing layer create a copper doping of the stabilizing layer. The provision of the copper layer adjacent the stabilizing layer and the migration of copper into the latter is herein referred to as “copper annealing”.

Preferably however, the layer stack with the copper layer on top (i.e. substrate/ back- electrode layer/ hole transport layer/ stabilizing layer/ copper layer) is subjected to

6 | U504697 an annealing step, before depositing the absorber layer. The annealing is preferably performed at a temperature of 400 to 600°C, preferably between 450 and 550°C, in particular about 500°C; typically under vacuum. The annealing duration may be between 5 and 30 min, in particular between 10 and 20 min. The skilled person will adapt the annealing step depending on the thickness and stabilizing layer composition. Such copper annealed step is believed to be beneficial to improve the conductivity of the stabilizing layer; it is also believed that copper diffusion into the stabilizing layer is promoted by the annealing step, and hence already starts during annealing.

In the case of copper annealed stabilizing layers, the copper concentration may be between 1 and 30 wt. %.

In the absence of copper annealing step, where the hole transport layer contains copper, the copper concentration in the stabilizing layer may be of less than 1 wt. %, possibly less than 0.1 wt.%

The semiconductor absorber layer is a layer of p-type chalcogenide material. It may be directly formed on the hole transport structure (i.e. on the stabilizing layer) or on the (intermediate) copper layer for copper annealing purposes, if such is provided.

In embodiments, p-type semiconductor chalcogenide materials that may be used for forming the absorber layer include without limitation CIGS compounds in general.

Exemplary materials for the absorber layer are Cu(ln,Ga)Se2, Ag(In,Ga)Se2,

Cu(In,Al)Se2, Cu(In,Ga)(Se,S)2, CulnSe2, CuGaSe2, CulnS2, and Cu(In,Ga)S2 or other elements of group Il, Ill or VI of the periodic table. In embodiments, the absorber layer comprises or consists of CulnSe2 and/or Cu(In,Ga)Se2. Other suitable chalcogenide materials may be used including without limitation

Cu(In,Ga)(Se,S)2, CuGaSe2, CulnS2, Cu(In,Ga)Se2 and Cu(In,Ga)S2.

The absorber layer may have a thickness ranging from about 0.1 um up to 3 um.

It may be noted that the absorber layer can be formed as a homogeneous layer, since thanks to the hole transport structure, no Ga gradient is required. Hence the absorber layer is advantageously exempt of Ga gradient. Consequently, the absorbed can also be manufactured with a lower thickness, e.g. of less than 1 um, i.e. forming a sub-micron CIGS solar cell.

Suitable conventional materials that may be used for the substrate layer include without limitation glass (including e.g. soda lime glass), ceramic, metals (including e.g. thin sheets of stainless steel and aluminium), or flexible polymers (including e.g. polyamides, polyethylene terephthalates, polyethylene naphthalates, polymeric hydrocarbons, cellulosic polymers, polycarbonates, polyethers, and others).

In embodiments, the back-electrode layer is a metallic layer, such as e.g. a layer of molybdenum, or a layer of transparent conductive oxides. Possible TCO are ZnO,

ZnO:Al, INOX:H, InOx:W, however other suitable electrically conductive metallic and semiconductor materials conventionally used in the art may be used such as e.g.

Al, Ag, Sn, Ti, Ni, stainless steel, or ZnTe.

The thickness of the back-electrode layer may typically depend on the metal and cell design; it may in general have a thickness ranging from about 50 nm to 1 um.

For a molybdenum layer, the thickness may range from 100 nm to 500 nm.

The upper structure of the solar cell, i.e. above the absorber layer (opposite the hole transport structure) can be conventionally designed. Typically, an electron transport layer (often referred to as buffer layer) and a top electrode layer are provided on the absorber layer. As is known, the layers provided on top of the absorber layer are transparent. Other conventional layers can be provided on or in between these layers, e.g. one or more window layer can be provided between the electron transport layer and the top electrode layer.

In embodiments, a sodium containing layer may be formed between the hole transport layer and the stabilizing layer, e.g. by thermal evaporation of a Na containing compound or from a solution containing a sodium salt. As is known in the art, sodium tends to have a positive effect on chalcogenide materials.

According to another aspect, there is provided a thin film solar cell comprising: a substrate; a back-electrode layer on the substrate; a hole transport structure on the back-electrode layer comprises a hole transport layer comprising p-type conductive material;

a semiconductor absorber layer on the back-electrode layer, the absorber layer comprising chalcogenide material; a window layer on the semiconductor absorber layer; and a top electrode layer on the window layer, wherein said hole transport structure further comprises a stabilizing layer on said hole transport layer, said stabilizing layer comprising a metal oxide and/or metal nitride.

Compositions/ features of the various layers have been disclosed above in relation to the inventive method and are thus applicable mutatis mutandis.

It should be noted that, in the present disclosure, unless explicitly stated that a particular layer is deposited directly on the underlying layer, it is possible that one or more intermediate layers can also be present between the layers mentioned. As a result, "on" should be construed by default as meaning "directly or indirectly on".

Furthermore, unless specifically stated, layers are not to be presumed as being 100% pure. Contaminants, other components, and so on can of course also be present, provided that the layer predominantly retains the properties of the composition mentioned, such as by comprising at least 50% of the substance mentioned, or at least 70%, 80%, 90%, 95% or 99%.

Brief Description of the Drawings

Further details and advantages of the present invention will be apparent from the following detailed description of not limiting embodiments with reference to the attached drawings, wherein:

Fig.1 is a principle diagram of an embodiment of the present solar cell;

Fig.2 is a principle diagram of a manufacturing step of the present solar cell according to another embodiment;

Fig.3 are SEM (scanning electron microscopy) cross-section images of the thin film solar cell of the first embodiment, before and after depositing the absorber layer;

Fig.4 is a plot of current density-voltage curves for examples 1-3 and comparative example 1;

Fig.5 is a graph of fill factors (FF) for same examples;

Fig.6 is a graph showing the open circuit voltage Voc for same examples;

Fig.7 is a plot of EQE (external quantum efficiency) as a function of wavelength;

Fig.8 are graphs representing the band diagram for example 1, which depicts the preferable conduction band offset between the HTL structure and the absorber is greater than 0.3 eV, and valance band offset is lower than 0.2 eV; and

Fig.9 shows images of the cell of example 1 as manufactured, where (a)is a TEM view, (b) are STEM views; and (c) to (h) show EDS mappings illustrating the position of the various elements in the layer stack.

Description of Preferred Embodiments

A first embodiment of the present thin film solar cell 10 is shown in Fig.1. In general, the solar cell 10 includes a substrate 12 that supports/carries a photovoltaic (or PV) stack 30. The PV stack 30 includes, in this order: a back-electrode layer 14, a hole transport layer 16, a stabilizing layer 18, an absorber layer 22, a buffer layer 24, and a window layer 26. Although not shown, a top electrode layer is typically arranged above the window layer.

The PV stack 30 is the core of the solar cell. Layers 16-26 constitute functional layers of the solar cell, required to implement the selected solar cell technology. The hole transport layer and the stabilizing layer form a hole transport structure 20 at the back electrode.

Additional layers may be formed on the window layer (preferably below the top electrode layer), such as e.g. a decorative layer and possibly a protective layer (not shown) on top of the decorative layer.

The PV stack 30 is conventionally designed as a layer stack, wherein each material layer covers entirely the underlying layer (although in embodiments one or more layers can be arranged as patterned layers, in particular the absorber). In other words, the back-electrode layer is continuous over an area of the substrate’s support surface and the layers 16 to 26 are continuous, vertically piled on top of another, over the same area of the back-electrode layer 14.

The focus of the present invention is the hole transport structure at the interface with the back electrode, which will be discussed in detail.

The layers on the opposite side of the absorber layer may be of any appropriate type and will therefore not be discussed in detail.

Substrate

The substrate is the base layer, which supports the various functional layers of the solar cell.

The substrate may be made from opaque or light transparent, typically selected from glass (or quartz), metal (e.g. titanium or steel) or polymer (e.g. PET, polystyrene, polyimide). It can take the form of a rigid plate or blade, or of a flexible foil (e.g. a thin polymer or metal foil), which has the advantage of flexibility.

The present thin film solar cell can be implemented in two structures, known as superstrate and substrate, depending on the direction through which light enters the cell.

In superstrates, the light enters the cell through the substrate base, on which the cell layers are deposited. For substrate structures however, the light does not pass through the base, but rather from the opposite side, i.e. from the window layer side.

Thus, for superstrate cells, the supporting substrate must be reasonably light transparent, as to allow enough light pass into the cell. Whereas metallic substrates can only be used in the substrates structure due to their opacity, polymers may be used in both structures, depending on their transparency.

The present thin film solar cell may also be combined vertically with another solar cell of same or different design.

As an end product, a solar panel or solar module comprises a multiplicity of adjacent solar cells arranged in a same plane.

Back electrode layer

The back electrode layer is typically a metallic layer, such as a layer of molybdenum, or a layer of transparent conductive oxides, preferably a layer of Indium-Tin Oxide or a layer of Tin-Zinc Oxide, however other suitable electrically conductive metallic and semiconductor materials conventionally used in the art may be used such as

Al, Ag, Sn, Ti, Ni, stainless steel, or ZnTe.

The back-electrode layer can be formed on the substrate layer by any conventional method commonly used in the art including without limitation sputtering, atomic layer deposition (ALD), chemical vapor deposition (CVD), or other techniques.

The back-electrode may in particular be a molybdenum layer having a thickness between 100 and 500 nm.

Hole transport structure

According to the present disclosure, a hole transport structure is provided between the back-electrode layer and absorber layer, which comprises a hole transport layer on the back electrode layer and a stabilizing layer on the hole transport layer.

Hole transport layer

The hole transport layer is a hole selective layer, which comprises p-type conductive material, and is directly formed on the back-electrode layer in the embodiment of

Fig.

In particular, the hole transport layer comprises or consists of p-type chalcogenide material. For example, the hole transport layer comprises or consists of a material selected from the group consisting of Cu(In,Ga)Se2, Cu(In,Ga)(Se,S)2, CulnSe2,

CuGaSe2, CulnS2, Cu(In,Ga)S2, (Cux, Ag1-x)(Gay, Al-y)(Sz,Se1-z2)2 and their mixtures.

For improved conductivity, the hole transport layer preferably is a Cu rich layer. In particular, the mass ratio Cu/Ga is preferably greater than 1.

The thickness of the HTL may range from 30 nm to 200 nm.

Stabilizing layer

The stabilizing layer is formed over the hole transport layer. In this embodiment the stabilizing layer is formed directly on the hole transport layer, but in other embodiments one (or more) intermediate layer may be present.

The stabilizing layer acts as barrier or passivating layer, since it will typically prevent the diffusion/migration of atoms of the HTL towards the absorber layer, during fabrication of the solar cell. Indeed, during the deposition of the absorber layer the layer stack is heated to relatively high temperatures, generally about 590°C).

The stabilizing layer is formed as a separate layer, distinct from the HTL, and remains so during the following cell manufacturing steps. First tests have shown that the thickness of the hole transport structure does not substantially change during deposition of the absorber layer.

The stabilizing layer is a layer of metal oxide or metal nitride, made from material having p-type conductivity. Typically, the stabilizing layer is a p-type semiconductor material(s), possibly doped to enhance conductivity, e.g. through Copper annealing.

The stabilizing layer preferably has a conduction band minimum (CBM) greater than the absorber layer, preferably by at least 0.3 eV compared to absorber material. The offset in conduction band is e.g. illustrated in Fig. 8, for a hole transport structure formed from CuGaSe2 and In203, over a CISe absorbed, as in example 1 below.

As seen in detail graph on the left, the In203 layer has a conduction band minimum that is 0.3eV above CISe absorber.

Typically, the stabilizing layer consists of a same metal oxide, although combinations can be envisaged.

The stabilizing layer may consist of a metal sesquioxide or of a metal dioxide. For example, the stabilizing layer may comprise a metal oxide selected from the group comprising Al203, Ga203, In203, TiO2, MoO2, SnO2, HfO2, and their mixtures.

Non-stoichiometric oxides of those metals are also possible.

The thickness of the stabilizing layer may range from 10 nm to 100 nm.

13 | U504697

It should be noted that in practice, due to the high temperatures involved by the absorber deposition step, some interdiffusion between the two layers 16 and 18 of the hole transport structure 20. That is, some atoms may move from the electron transport layer 16 to the stabilizing layer 18, and inversely. However, the two layers remain with essentially same thickness and the stabilizing passivating effect is conformed (see below).

The migration between layers is illustrated e.g. on Fig.9, for a solar cell formed by depositing the following layers (corresponding to example 1 below): Mo electrode;

CuGaSe2 hole transport layer; In203 stabilizing layer and CulnSe2 absorber.

As can be seen, Ga tends to move up to the stabilizing layer, whereas In has moved down to the hole transport layer. However, oxygen remains in the stabilizing layer and Ga did not migrate to the absorber layer. Small amounts of copper can be found in the stabilizing layer, typically below 1 wt. %.

As a result, whereas we have described above composition of the layers 16 and 18 at the time they are deposited, their composition may be modified during the subsequent manufacturing steps. Nevertheless, it can be observed that some atom species may diffuse/migrate, they rest within the hole transport structure 20.

The composition of the layers of the hole transport structure 20 in the manufactured solar cell hence depends on the composition of the layers as formed.

This being said, in general the stabilizing layer in the manufactured cell comprises compounds such as MNx, MOx and/or MNxOy, where M is a metal (however there can be different metals), and x and y can be integers (stoichiometric compound) or decimal values (non-stoichiometric). The metal is preferably one of Si, Al, Ga, In, Ti and Hf. There can be oxides and nitrides of different metals. The hole transport layer remains a p-type chalcogenide, despite possible diffusion effects.

Absorber layer

The absorber layer is the base photovoltaic material, which absorbs the majority of the sunlight coming from outside the cell (through the adjacent layers). The absorber layer includes p-type chalcogenide material configured to exhibit a photovoltaic effect, whereby absorption of the incident light excites the charge carriers.

The chalcogenide material of the absorber layer may generally have bandgap between 0.8 and 2.4 eV, in particular between 1 and 1.7 eV.

Any appropriate absorber material can be used in the context of the invention.

Exemplary materials for the absorber layer include chalcogenides such as CIGS - (Ag,Cu)(In,Ga)(S,Se)a (copper indium gallium chalcogenide and its silver alloys),

CdTe (cadmium telluride and its alloys), kesterites such as (Ag,Cu)2Zn(Sn,Ge)(S,Se)s (copper zinc tin sulfide and its alloys), (Bi,Sb)2(S,Se)s antimony chalcogenide and its alloys..

For CIS/CIGSe materials, the absorber layer may have a thickness between 50 to 3500 nm, where typically it is between 2000 to 3500 nm, and in embodiments between 100 and 500 nm.

The absorber layer can be deposited using common processes such as selenization and co-evaporation. Other methods are however also possible such as evaporation, sputtering, electrodeposition, chemical vapor deposition, or ink spraying.

Upper stack layers

The upper layers can be of conventional design. As indicated above, they typically comprise at least the buffer layer, window layer and electrode layer.

The buffer layer is designed as electron transport layer and comprises n-type semiconductor material so as to form a thereby creating an electrically active p-n junction with the absorber layer.

The buffer layer 24 may conventionally be a CdS layer (typically deposited by chemical bath), or made from any other suitable material, such as e.g. Zn(O,S).

The window layer 26 may conventionally be a i-ZnO/Al:ZnO double window layer, as is known in the art, which may be deposited by sputtering.

The ZnO layer is intrinsically doped and permits the electron conduction through the conduction-band. The Al:ZnO is transparent conducting oxide (TCO).

Other options for the window layer are, e.g., ZnO, ZnO:Al, Zn:B, ITO, InOx:H,

INOX:W.

The electrode layer can typically take the form of Ni-Al grids, which can be deposited in sequence via e-beam evaporation or generally PVD.

Other layers can be added, if desirable. For example, a layer of low index materials such as MgF2 can be evaporated at the surface of the ZnO:AI to reduce the light reflection at the air/ZnO:AI interface.

Those skilled in the art may adapt the upper structure of the solar cell as appropriate, depending on desired properties and in relation with particular applications.

Manufacturing processes

The present solar cell can be manufactured using known thin film fabrication techniques, i.e. which allow depositing a thin layer of material onto a substrate or onto previously deposited layers, including inter alia, chemical deposition processes such as e.g. chemical solution deposition, chemical bath deposition, spin coating, dip coating, chemical vapor deposition, physical deposition processes such as e.g. evaporation processes, electron beam evaporation, molecular beam epitaxy, sputtering, pulsed laser deposition, or printing processes.

Deposition techniques are indicated hereinabove for each layer, however only on an exemplary basis. Those skilled in the art may generally select the appropriate layer deposition technique depending on the material in the layer.

Having regard to the first embodiment, and in reference to Fig.1, the manufacturing process of the solar cell involves using appropriate deposition process (or generally layer forming process), to form the stack 30 over the substrates. The layers 14, 16, 28, 22, 24 and 26 are deposited in sequence, one after another, over the substrate 12, starting with layer 14.

Effects of the invention

The present invention aims to improve the efficiency of thin film solar cells. In the

CIGS solar cells, the Ga grading plays a critical role in mitigating back surface recombination and achieving high efficiency. However, the drawbacks of the inhomogeneous absorber have been discussed in the literature, mostly a higher radiative loss and insufficient absorption. Therefore, a paradigm shift has been called for which relies on the passivation of the back contact by a suitable hole transport layer, which must be able to withstand the harsh environment of the chalcopyrite deposition process.

The present disclosure provides a solar cell structure and corresponding manufacturing process, that includes a stable hole transport structure with a passivation effect similar to the one of Ga grading. This hole transport structure comprises a p-type semiconductor hole transport layer, over which a metal oxide layer is formed, acting as stabilizing layer blocking the diffusion of the hole transport layer. By introducing this double layer structure, the issue of thermal stability is effectively overcome.

Second embodiment

In a second embodiment, the manufacturing includes comprises the step of depositing copper layer 21, also referred to as intermediate layer, adjacent the stabilizing layer 18.

This is shown in Fig.2, where the copper layer 21 is deposited on top of the stabilizing layer 18. Alternatively, the copper layer may be formed (directly) in- between the hole transport layer and the stabilizing layer.

During absorber deposition, copper atoms will diffuse into the stabilizing layer 18, causing an enrichment or doping of the stabilizing layer 18 with copper atoms.

Without willing to be bound by any theory, it is believed that copper atoms diffusing into the stabilizing layer 18 can create defects in the layer structure than can facilitate the passage of holes, or globally improve the conductivity of the stabilizing layer 18.

The copper layer may be deposited with a thickness similar to the stabilizing layer, e.g. 10to 100 nm.

The deposited copper layer is preferably subjected to an annealing treatment. For example, copper annealing can be carried out at a temperature between 400 and 500°C, under vacuum, for a duration of 15, 20, 25 or 30 min.

In practice, the copper layer can be dissolved in part, or entirely (already confirmed by first experiments). Hence, the copper layer illustrated in Fig.2 may no longer exit in the solar cell as manufactured, which therefore has a structure as shown in Fig.1.

During absorber deposition, the copper layer may disappear (be dissolved) in part orentirely, due to copper migrating towards the barrier layer and the absorber layer.

Where the copper layer entirely disappears, the resulting structure is the same as in Fig.1. However, compared to the first embodiment, the stabilizing layer is enriched with copper, and may thus be referred as ‘copper doped’ or ‘copper annealed’ layer.

Exemplary embodiments

Samples preparation

Example 1 - Thin film solar cell

Substrate layer: a glass layer with a thickness of 2 mm.

Back electrode layer: a 500 nm thick molybdenum layer is prepared by sputtering.

Hole transport layer: CuGaSe2 layer. A 100 nm thick CuGaSe2 layer is deposited by co-evaporation with a substrate temperature of 365°C.

Stabilizing layer: a In203 layer is prepared by solution combustion synthesis (SCS).

In203 combustion solution is prepared by dissolving 1203.2 mg of In(NO3)3-xH20 (99.99%, Sigma-Aldrich) in 20 mL of 2-methoxyethanol (2-MOE, 99.8%, Sigma-

Aldrich) to form 0.2 M solutions. 800 uL of acetylacetone (C5H802, Sigma-Aldrich, 99%) is added as a fuel to the solutions. 90 mL of 14.5 M NH3 (aqueous, 99%,

Sigma-Aldrich) for per mmol In ions is added to raise the pH and promote the formation of In(acac)x (acac = C5H702) complexes of In ions. The solutions are then stirred until they became clear. With this clear solution, the In203 films are prepared by spin coating the solutions at 3000 rpm for 60 s on the substrates, followed by hot-plate heating at 130°C for 1 min. The process of spin-coating-drying is repeated four times to achieve 50 nm thickness. Finally, the crystallization of films is performed by placing the samples on hot-plate in air with the setting temperature varying from 200 to 350°C for 3 min. The Ga203 is prepared by the same method

18 | U504697 and procedure, the only difference is replacing In(NO3)3-xH20 (99.99%, Sigma-

Aldrich) by Ga(NO3)3-xH20 (99.99%, Sigma-Aldrich).

Absorber layer: a CulnSe2 absorber layer is prepared with a typical 3-stage process.

At the first stage, the InSe precursor is formed with a low substrate setting temperature of 365 °C. At the second stage, the Cu and Se are added to the film with a substrate temperature of 570 °C. When it becomes slightly Cu rich (Cu/In = 1.05), the Cu shutter is closed and the film is annealed in a Se atmosphere for 20 minutes. At the third stage with the same substrate setting temperature of 570°C, In and Se are supplied again to make the final absorber slightly Cu poor (Cu/In = 0.95) with a thickness of ~1.8 um and bandgap of 1.01 eV. The substrate temperature read from the pyrometer is usually lower than the setting temperature. The setting temperature is higher, the temperature difference is larger. For the low temperature, e.g. 365 °C, they are more or less the same. For the high temperature, e.g. 570 °C, the temperature from the pyrometer is 50~60°C lower than the setting temperature.

Buffer layer: a CdS layer is prepared by chemical bath deposited (CBD). Before CdS covering, all samples are chemically etched with 5% aqueous KCN solution for 30 s to remove potential residual oxides. The CBD recipe is 6-7 min deposition at 67 °C with 2 mM CdS 04, 50 mM thiourea and 1.5 M NH40H. The estimated thickness is 40-50 nm according to typical growth rates. The CdS is necessary to passivate the front surface and prevent surface degradation during the PL characterization.

Window layer and top electrode layer: To finish the devices, the i-ZnO/AI:ZnO are sputtered on the top of the CdS followed by e-beam evaporated Ni/Al grids.

Example 2 - Thin film solar cell

The thin film solar cell is prepared in the same way as example 1, with the difference that a thin layer having a thickness of about 4 nm of NaF is deposited by thermal evaporation between the two layers of the hole transport structure, i.e. between the

CuGaSe2 layer and the In203 layer.

Example 3 - Thin film solar cell

A thin film solar cell is prepared in the same way as example 1, using an absorber of Cu(ln, Ga)Se2 with a thickness of 900 nm and bandgap of 1.15 eV

In terms of manufacturing process however, an additional Cu layer is deposited on the stabilizing layer (In203) before forming the absorber layer. This Cu layer has a thickness similar to the stabilizing layer, here of about 50 nm.

Then the whole stack(Glass/Mo/CuGaSe2/In203/Cu) is heated up to 500 °C with a rate of 50 °C /m under high vacuum of 107-10"° mtorr, and annealed with the temperature of 500 °C for 20 minutes. Then it is cooled down to 200 °C with a rate of 20~30 °C /m under the same vacuum.

The copper layer is completely dissolved and cannot be observed in the manufactured solar cell.

Comparative example 1 - Reference thin film solar cell

A reference cell is manufactured with following structure: substrate/Mo back- electrode/ CulnSe2 /CdS/ i-ZNO/AI:ZnO.

That is, there is no hole transport structure (CuGaSe2/In203).

The various layers are deposited using the same sample preparation processes as for example 1.

Samples characterization lllumination current density-voltage (J-V)

Measurements were carried out at 25 °C with a 4-probe configuration. A class AAA solar simulator supplies a simulated AM1.5G spectrum that is calibrated by a Si reference cell. The forward scanning voltage is applied from -0.3 V to 0.6 V with a step of 0.01 V.

Scanning electron microscope (SEM)

Scanning electron microscope is used to analyze the cross-sectional microstructures of the films.

External Quantum Efficiency determination

20 | U504697

To measure the external quantum efficiency (EQE), chopped illumination from a halogen/xenon lamp is used and a lock-in amplifier is utilized to accurately measure the photocurrent

Experimental results

In Figs.4 to 6, the results correspond to examples 1 to 3 and comparative-example 1, and are indicated as follows: — “a” corresponds to comparative example 1, also noted Mo-Re — “b” corresponds to example 1, also noted HTL — “c’ corresponds to example 2, also noted HTL+NaF — “d” corresponds to example 3, also noted HTL+Cu annealing

SEM cross-section images (Fig.3) relates to example 1 (Mo/ CuGaSe2/ CuGaSe2/

CulnSe2) and clearly shows that the initial thickness of In203 and CuGaSe2 before the CulnSe2 deposition is around 50 nm and 100 nm respectively. After the

CulnSe2 absorber deposition, the individual structure of two layers can still be easily identified, and their respective thicknesses remain unchanged, which confirms that

In203 is a good stabilizer that blocks massive out-diffusion of Ga.

The passivating effect of the new HTL is also demonstrated by the external quantum efficiency (EQE) spectra (Fig. 7). Compare the thin film solar cell according to example 2 (Na doping) with a solar cell without the present hole transport structure, namely with direct Mo back contact solar cell (comparative example 1) and here with an additional comparative example corresponding to a cell with a Ga gradient in the absorber (indicated GBG).

The inventive thin film solar cell has the best EQE response to long wavelength photons, meaning the best collection of long wavelength photon generated carriers, thus the best backside passivation.

The steepest onset of absorption and collection (lowest inflection point) is observed for the thin film solar cell according to the invention (Fig. 7). The reference thin film solar cell depicts a more gradual EQE edge because carriers generated near the back contact by long wavelength irradiation have a lower chance to be collected due

21 | U504697 to the vicinity of the high recombination active back contact. This loss is also reflected by an overall lower EQE. And the comparative solar cell has lower absorption for long wavelength irradiation than the inventive solar cell: the low bandgap region is considerably thinner than the whole film thickness. À gradual onset of absorption leads to additional radiative voltage losses.

Moreover, no obvious hole transport or current blocking behaviors are observed in the current density - voltage characteristics (Fig.4), which leads to a quite good FF of more than 71% (Fig. 5). This observation clearly indicates that inventive thin film solar cell with a hole transport structure comprising a layer of CuGaSe2 and a layer of In203 has sufficient hole selectivity to keep high Voc (Fig. 6) and FF at the same time.

Adding NaF can improve the Voc (Fig. 6) since Na is an important dopant to CIGS.

With Cu annealing, the Cu annealed sample 3 has an even higher FF of 77 % (Fig. 5), meaning the Cu annealing can improve the hole transport property.

The high Voc of sample 3 (Fig.6) compared to its bandgap (1.15 eV) proves the good passivation effects of Cu-annealed hole transport structure.

Claims

1. A method for producing a thin film solar cell comprising the steps of: providing a substrate (12); forming a back-electrode layer (14) on said substrate; forming a hole transport structure (20) on said back electrode layer, said hole transport structure comprising a hole transport layer (16) comprising p-type conductive material on said back-electrode layer and a stabilizing layer (18) on said hole transport layer, said stabilizing layer comprising a metal oxide and/or a metal nitride; and forming a semiconductor absorber layer (22) on said hole transport structure, said absorber layer comprising chalcogenide material.

2. The method as claimed claim 1, wherein said stabilizing layer comprises metal oxides and/or metal nitrides of one or more metals selected from the group comprising Si, Mo, Al, Ga, In, Ti and Hf.

3. The method as claimed in claim 1 or 2, wherein said stabilizing layer is deposited as a metal oxide selected from the group comprising Al203, Ga203, In203, TiO, MoOz, and their mixtures.

4. The method as claimed in any one of claims 1 to 3, wherein the stabilizing layer has a thickness between 10 and 100 nm.

5. The method as claimed in any one of the preceding claims, wherein a conduction band minimum of the stabilizing layer is greater than that of the absorber layer, preferably by at least 0.3 eV.

6. The method as claimed in any one of the preceding claims, wherein the hole transport layer comprises p-type chalcogenide material.

7. The method as claimed in claim 6, wherein the hole transport layer comprises a material selected from the group consisting of Cu(In,Ga)Se2, Cu(In, Ga)(Se,S)2, CulnSe2, CuGaSe2, CulnS2, Cu(In,Ga)S2 and their mixtures.

8. The method as claimed in any one of the preceding claims, wherein the hole transport layer has a thickness of between 30 and 200 nm.

9. The method as claimed in any one of the preceding claims, wherein the absorber layer comprises, preferably consists of, a material selected from the group consisting of Cu(In,Ga)Se2, Cu(Iln,Ga)(Se,S)2, CulnSe2, CuGaSe2, CulnS2, Cu(In,Ga)S2 and their mixtures.

10. The method as claimed in any one of the preceding claims, wherein the absorber layer has a thickness of 0.1 to 3 um.

11. The method as claimed in claim any one of the preceding claims, wherein forming said hole transport structure includes forming a copper layer (21) adjacent said stabilizing layer.

12. The method as claimed in claim 11, comprising annealing the layer stack with said copper layer (21) on top at a temperature between 400 and 600°C, preferably between 450°C and 550°C, in particular about 500°C, for a time period between 5 and 30 min, in particular between 10 and 20 min.

13. The method as claimed in claim 11 or 12, wherein said copper layer has a thickness similar to said stabilizing layer.

14. The method as claimed in any one of the preceding claims, comprising depositing a sodium layer between the hole transport layer and the stabilizing layer.

15. The method as claimed in the preceding claim, further comprising the steps of — forming an electron transport layer above the absorber layer; and — forming a top electrode layer above the electron transport layer.

16. A thin film solar cell comprising: a substrate (12); a back-electrode layer (14) on said substrate; a hole transport structure (20) on said back-electrode layer, said hole transport structure including a hole transport layer (16) comprising p-type conductive material; a semiconductor absorber layer (22) on said hole transport structure, said absorber layer comprising chalcogenide material;

an electron transport layer (24) on the semiconductor absorber layer; and a top electrode layer (26) on the electron transport layer, wherein said hole transport structure (20) further comprises a stabilizing layer (18) on said hole transport layer (16), said stabilizing layer comprising a metal oxide and/or a metal nitride.

17. The thin film solar cell as claimed in clam 16, wherein said stabilizing layer comprises metal oxides and/or metal nitrides of one or more metals selected from the group comprising Si, Mo, Al, Ga, In, Ti and Hf.

18. The thin film solar cell as claimed in claim 16 or 17, wherein the stabilizing layer has a thickness between 10 and 100 nm.

19. The thin film solar cell as claimed in any one of claims 16 to 18, wherein a conduction band minimum of the stabilizing layer is greater than that of the absorber layer, preferably by at least 0.3 eV.

20. The thin film solar cell as claimed in any one of claims 16 to 19, wherein the stabilizing layer is a copper annealed layer.

21. The thin film solar cell as claimed in any one of claims 16 to 20, wherein the hole transport layer comprises p-type chalcogenide material.

22. The thin film solar cell as claimed in claim 21, wherein the absorber layer comprises a material selected from the group consisting of Cu(ln,Ga)Se2, Cu(In,Ga)(Se,S)2, CulnSe2, CuGaSe2, CulnS2, Cu(In,Ga)S2 and their mixtures.

23. The thin film solar cell as claimed in any one of claims 16 to 22, wherein the absorber layer has a thickness of between 0.1 um to 3 um.

24. The thin film solar cell as claimed in any one of claims 16 to 23, wherein the back-electrode layer is a metal layer, preferably a layer of Mo, or a layer of transparent conductive oxide.

25. A thin film solar module comprising a multiplicity of thin film solar cells according to any one of claims 16 to 24.