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KR980006287A - How to arrange cell blocks and pads in memory devices - Google Patents

How to arrange cell blocks and pads in memory devices Download PDF

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Publication number
KR980006287A
KR980006287A KR1019960025807A KR19960025807A KR980006287A KR 980006287 A KR980006287 A KR 980006287A KR 1019960025807 A KR1019960025807 A KR 1019960025807A KR 19960025807 A KR19960025807 A KR 19960025807A KR 980006287 A KR980006287 A KR 980006287A
Authority
KR
South Korea
Prior art keywords
cell blocks
pads
cell block
memory devices
memory device
Prior art date
Application number
KR1019960025807A
Other languages
Korean (ko)
Inventor
허천신
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960025807A priority Critical patent/KR980006287A/en
Publication of KR980006287A publication Critical patent/KR980006287A/en

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  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

본 발명은 메모리 소자에서 셀 블럭과 패드 배열 방법에 관한 것으로, 메모리 셀 블럭에 배치되는 패드의 배열을 셀 블럭과 셀 블럭의 사이에 배치시키고, 복수개의 셀 블럭들이 입/출력 버스 라인 및 주변회로를 공유하지 않고 독립적으로 연결될 수 있도록 하므로써, 버스라인들의 부하를 감소시켜 메모리 소자의 동작속도를 향상시키는 잇점이 있다.The present invention relates to a cell block and a pad arrangement method in a memory device, in which the arrangement of pads arranged in a memory cell block is arranged between a cell block and a cell block, and a plurality of cell blocks are connected to the input / So that the load of the bus lines is reduced, thereby improving the operation speed of the memory device.

Description

메모리 소자에서 셀 블록과 패드 배열 방법How to arrange cell blocks and pads in memory devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제 3도는 본 발명에 의해 구현된 리드 온 칩 패키지의 셀 블록과 패드 배열을 나타내는 구조도FIG. 3 is a structural view showing a cell block and pad arrangement of a lead-on-chip package implemented by the present invention;

Claims (1)

주변회로 및 입/출력 버스를 복수개의 셀 블럭이 공유하도록 배치된 메모리 소자의 셀 블럭 및 패드 배열 방법에 있어서, 일정용량의 셀 블럭을 분할하고, 상기 셀 블럭과 셀 블럭의 가로 방향 사이에 패드를 배열하며, 상기 복수개의 셀 블럭 각각에 입/출력 버스라인이 일대일 대응되도록 상기 패드의 양측으로 배치하고,상기 복수개의 셀 블럭 각각에 주변회로를 배치하여 독립적으로 연결되도록 하므로써, 셀 블럭 내의 워드라인과 데이터 버스 라인의 부하를 줄여 메모리 소자의 동작속도를 향상시키는 것을 특징으로 하는 메모리 소자의 셀 블럭과 패드 배열 방법.A method of arranging a cell block and a pad in a memory device in which a peripheral circuit and an input / output bus are shared by a plurality of cell blocks, the method comprising the steps of: dividing a cell block having a predetermined capacity; Output bus lines are arranged on both sides of the pads so that the input / output bus lines correspond to each other in a one-to-one correspondence to the plurality of cell blocks, and peripheral circuits are arranged in each of the plurality of cell blocks to be independently connected, And reducing the load on the line and data bus lines to improve the operating speed of the memory device.
KR1019960025807A 1996-06-29 1996-06-29 How to arrange cell blocks and pads in memory devices KR980006287A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960025807A KR980006287A (en) 1996-06-29 1996-06-29 How to arrange cell blocks and pads in memory devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960025807A KR980006287A (en) 1996-06-29 1996-06-29 How to arrange cell blocks and pads in memory devices

Publications (1)

Publication Number Publication Date
KR980006287A true KR980006287A (en) 1998-03-30

Family

ID=66241037

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960025807A KR980006287A (en) 1996-06-29 1996-06-29 How to arrange cell blocks and pads in memory devices

Country Status (1)

Country Link
KR (1) KR980006287A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6300651B1 (en) 1998-05-20 2001-10-09 Nec Corporation Chip layout for symmetrical-critical elements

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6300651B1 (en) 1998-05-20 2001-10-09 Nec Corporation Chip layout for symmetrical-critical elements
KR100326823B1 (en) * 1998-05-20 2002-03-04 가네꼬 히사시 Semiconductor device

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Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19960629

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid