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KR970071788A - Output stage placement to reduce output skew - Google Patents

Output stage placement to reduce output skew Download PDF

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Publication number
KR970071788A
KR970071788A KR1019960010217A KR19960010217A KR970071788A KR 970071788 A KR970071788 A KR 970071788A KR 1019960010217 A KR1019960010217 A KR 1019960010217A KR 19960010217 A KR19960010217 A KR 19960010217A KR 970071788 A KR970071788 A KR 970071788A
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KR
South Korea
Prior art keywords
output
skew
group
pads
reduce
Prior art date
Application number
KR1019960010217A
Other languages
Korean (ko)
Inventor
유승문
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960010217A priority Critical patent/KR970071788A/en
Publication of KR970071788A publication Critical patent/KR970071788A/en

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Abstract

본 발명은 칩내에 동일한 출력을 위한 다수의 출력단을 배치하고 이의 연결을 칩내부가 아닌 칩외부에서 행함으로써, 출력단의 스큐를 최소화하고 저전력 및 어떠한 패키지 형태에 관계없이 적응이 가능한 출력 스큐를 줄이기 위한 출력단 배치방법에 관한 것인 바, 그 특징은 하나 이상의 그룹으로 나뉘어지는 다수 개의 메모리 배열을 가지며, 상기 메모리 배열의 각 그룹마다 출력을 외부로 전송하기 위한 다수의 동일한 출력 패드(51)(52)를 갖도록 배치함에 있다.The present invention is based on the idea of placing a plurality of output stages for the same output in a chip and connecting them outside the chip rather than inside the chip to minimize the skew of the output stage and to reduce the output skew for low power and adaptable to any package type The present invention relates to a method of arranging output stages having a plurality of memory arrays that are divided into one or more groups and having a plurality of identical output pads 51 and 52 for transmitting outputs to each group of the memory arrays, As shown in Fig.

Description

출력 스큐를 줄이기 위한 출력단 배치방법Output stage placement to reduce output skew

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제5도는 본 발명의 일 실시예에 따른 출력 스큐 최소화를 위한 출력단 배치구조도.FIG. 5 is an output stage layout structure for minimizing output skew according to an embodiment of the present invention; FIG.

Claims (5)

하나 이상의 그룹으로 나뉘어지는 다수 개의 메모리 배열을 가지며, 상기 메모리 배열의 각 그룹마다출력을 외부로 전송하기 위한 다수의 동일한 출력 패드(51)(52)를 갖는 것을 특징으로 하는 출력 스큐를 줄이기 위한 출력단 배치방법.And a plurality of output pads (51) (52) for transferring outputs to the outside for each group of the memory arrays, wherein the output pads (51) and (52) Placement method. 제1항에 있어서, 상기 각각의 그룹에 위치한 출력 패드의 수가 패키지의 출력 패드의 수와 같음을 특징으로 하는 출력 스큐를 줄이기 위한 출력단 배치방법.2. The method of claim 1, wherein the number of output pads in each group is equal to the number of output pads in the package. 제1항에 있어서, 상기 각각의 그룹마다 패키지 핀의 수와 동일한 데이타가 일시에 상기 그룹마다 배치된패드를 통해서 출력됨을 특징으로 하는 출력 스큐를 줄이기 위한 출력단 배치방법.2. The method according to claim 1, wherein the same data as the number of package pins for each group is output through a pad arranged for each group at a time. 제1항에 있어서, 상기 출력 패드의 연결이 다른 층의 패드를 가지고 이루어짐을 특징으로 하는 출력 스큐를 줄이기 위한 출력단 배치방법.2. The method of claim 1, wherein the connection of the output pads comprises pads of different layers. 제1항에 있어서, 상기 패드마다 할당된 핀이 존재하여 이들 핀이 같은 정보를 가진것끼리 연결됨을 특징으로 하는 출력 스큐를 줄이기 위한 출력단 배치방법.2. The method of claim 1, wherein the pins allocated to each of the pads are connected to each other so that the pins having the same information are connected to each other. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960010217A 1996-04-04 1996-04-04 Output stage placement to reduce output skew KR970071788A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960010217A KR970071788A (en) 1996-04-04 1996-04-04 Output stage placement to reduce output skew

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960010217A KR970071788A (en) 1996-04-04 1996-04-04 Output stage placement to reduce output skew

Publications (1)

Publication Number Publication Date
KR970071788A true KR970071788A (en) 1997-11-07

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960010217A KR970071788A (en) 1996-04-04 1996-04-04 Output stage placement to reduce output skew

Country Status (1)

Country Link
KR (1) KR970071788A (en)

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PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19960404

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid