KR970071241A - How to manage cache state (RAM) in multiprocessing systems - Google Patents
How to manage cache state (RAM) in multiprocessing systems Download PDFInfo
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- KR970071241A KR970071241A KR1019960011631A KR19960011631A KR970071241A KR 970071241 A KR970071241 A KR 970071241A KR 1019960011631 A KR1019960011631 A KR 1019960011631A KR 19960011631 A KR19960011631 A KR 19960011631A KR 970071241 A KR970071241 A KR 970071241A
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Abstract
본 발명은 프로세서가 캐시 영역을 억세스 했을때 캐시 미스가 발생하여 메인 메모리로부터 데이타를 읽어온 후 캐시 데이타 램에 기록하는 과정과 캐시 스테이트 램을 업데이트하는 과정을 효과적으로 관리하여 전체적인 시스템의 향상을 도모하도록 한 다중처리 시스템의 캐시 스테이트 램 관리방법에 관한 것이다.The present invention effectively manages the process of writing a cache miss when a processor accesses a cache area and reading data from the main memory, writing the data to the cache data RAM, and updating the cache state RAM, thereby improving the overall system To a cache state management method for a multi-processing system.
이러한 본 발명은 프로세서에서 사이클이 시작되면 캐시 데이타 램에 데이타가 존재하는지를 검색하는 제1과정과; 캐시 데이타 램에 데이타가 존재하는 경우 캐시 데이타 램에서 리드/라이트를 수행하고 사이클을 종료하는 제2과정과; 캐시데이타 램에 데이타가 비존재하는 경우 메인 메모리로부터 데이타를 읽어온 후 캐시 데이타 램에 그 읽어온 데이타를 기록함과 동시에 캐시 스테이트 램을 업데이트시키는 제3과정을 순차 실행시키게 되는 것이다.The present invention comprises a first step of detecting whether data is present in a cache data RAM when a cycle starts in a processor; A second step of performing read / write in the cache data RAM and terminating the cycle when data is present in the cache data RAM; A third step of reading the data from the main memory when the data is not present in the cache data RAM and then writing the read data in the cache data RAM and updating the cache state register at the same time.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제1도는 종래 다중처리 시스템의 블럭 구성도, 제2도는 종래 다중처리 시스템의 캐시 스테이트 램 관리과정 흐름도, 제3도는 본 발명이 적용되는 다중처리 시스템 블럭 구성도, 제4도는 본 발명에 의한 다중처리 시스템의 캐시 스테이트 램 관리과정 흐름도.1 is a block diagram of a conventional multiprocessing system, FIG. 2 is a flow chart of a cache state management process of a conventional multiprocessing system, FIG. 3 is a block diagram of a multiprocessing system block to which the present invention is applied, A flowchart of the cache state management process of a processing system.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960011631A KR970071241A (en) | 1996-04-17 | 1996-04-17 | How to manage cache state (RAM) in multiprocessing systems |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960011631A KR970071241A (en) | 1996-04-17 | 1996-04-17 | How to manage cache state (RAM) in multiprocessing systems |
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| Publication Number | Publication Date |
|---|---|
| KR970071241A true KR970071241A (en) | 1997-11-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960011631A KR970071241A (en) | 1996-04-17 | 1996-04-17 | How to manage cache state (RAM) in multiprocessing systems |
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| KR (1) | KR970071241A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100404374B1 (en) * | 1999-03-31 | 2003-11-05 | 인터내셔널 비지네스 머신즈 코포레이션 | Method and apparatus for implementing automatic cache variable update |
-
1996
- 1996-04-17 KR KR1019960011631A patent/KR970071241A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100404374B1 (en) * | 1999-03-31 | 2003-11-05 | 인터내셔널 비지네스 머신즈 코포레이션 | Method and apparatus for implementing automatic cache variable update |
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| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19960417 |
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| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |