KR970068173A - Decoding circuit built in frequency synthesizer - Google Patents

Abstract

The present invention relates to a decoding circuit incorporated in a frequency synthesizer, and more particularly to a decoding circuit incorporated in a frequency synthesizer which is operated so that a plurality of channels can be selected irrespective of a telephone channel specification of a telephone, The inverted signal of the least significant bit data signal and the least significant bit data signal from the channel data outputted from the microcomputer and the reference frequency signal divided by the reference frequency divider are inputted respectively to select signals of 10 channels and 15 channels And an output signal of the channel selection signal generation unit is inputted. The selection signal of 10 channels is outputted as a channel selection signal according to the channel selection input signal, or the selection signal of 15 channels is outputted as a channel selection signal And outputting the selected channel as a channel selection signal.

Description

Decoding circuit built in frequency synthesizer

Since this is a trivial issue, I did not include the contents of the text.

FIG. 2 is a circuit diagram showing an embodiment of a decoding circuit built in a frequency synthesizer according to the present invention, and a timing diagram therefor. FIG.

Claims (2)

A decoding circuit built in a frequency synthesizer, comprising: a programmable divider output frequency signal; a least significant bit data signal from the channel data output from the microcomputer; an inverted signal of the least significant bit data signal; A channel selection signal generation unit for receiving a reference frequency signal and outputting a selection signal of 10 channels and a selection signal of 15 channels, and an output signal of the channel selection signal generation unit, And a channel selector for allowing the selection signal to be output as a channel selection signal or for outputting a selection signal of 15 channels as a channel selection signal. 2. The semiconductor memory device according to claim 1, wherein the channel selection signal generator comprises: a first PMOS transistor having an inverted signal of the data signal of the least significant bit input to the gate electrode; and a second PMOS transistor having a common source electrode, A first NMOS transistor having an input terminal to which the output frequency signal of the programmable frequency divider is input and a data signal of the least significant bit is input to the gate electrode, a second NMOS transistor having an inverted signal of the data signal of the least significant bit input to the gate electrode, Wherein the reference frequency signal is input to the common source electrode, the data signal of the least significant bit is input to the gate electrode, and the drain electrode is connected to the second p-MOS transistor, And a second PMOS transistor connected to the drain electrode of the MOS transistor, The channel selection unit receives the output signal of the second PMOS transistor as an input signal, the inverted signal of the channel selection input signal is input to the gate electrode of the transistor to be processed, and the channel selection input signal is input And a gate electrode of the transistor is connected to the gate electrode of the transistor. The first selection gate signal and the first PMOS transistor output signal are input to the gate of the transistor, and the inverted signal of the channel selection input signal is input to the gate electrode of the transistor. A second transmission gate element to which an input signal is inputted and has a common output with the first transmission gate element and the output of the first and second NMOS transistors is connected to a common output; An output signal output from the common output of the device is input as an input signal, and the channel selection input A third transmission gate element into which the inverted signal of the input signal is inputted to the gate electrode of the transistor to be processed and the channel selection input signal is inputted to the gate electrode of the transistor, The channel selection input signal is input to the electrode, the inverted signal of the channel selection input signal is input to the gate electrode of the transistor, the common output is provided to the third transmission gate device, And a fourth transmission gate element for outputting a channel selection signal of the 15 channel selection signal. ※ Note: It is disclosed by the contents of the first application.