KR0119247Y1 - Decoder circuit - Google Patents
Decoder circuitInfo
- Publication number
- KR0119247Y1 KR0119247Y1 KR2019910023426U KR910023426U KR0119247Y1 KR 0119247 Y1 KR0119247 Y1 KR 0119247Y1 KR 2019910023426 U KR2019910023426 U KR 2019910023426U KR 910023426 U KR910023426 U KR 910023426U KR 0119247 Y1 KR0119247 Y1 KR 0119247Y1
- Authority
- KR
- South Korea
- Prior art keywords
- circuit
- high level
- inverter
- output
- decoder circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
Abstract
본고안은 펄스화된 출력을 필요로 하는 궤환형 디코더 회로에 관한 것으로 기존에는 어드레스 신호 입력이 하이레벨일 때 워드라인 신호는 항상 하이레벨을 유지하여 소비전력이 불필요하게 증가되었으나 본고안에서는 인버터(1)와 모스 트랜지스터(N1~ N4)사이에 궤환회로(2)를 구비하여 어드레스 신호 입력이 하이레벨일때에 워드라인 신호는 하이/로우를 반복하여 소비전력을 감소시킬 수 있게 하며 별도의 펄스화 회로를 사용하지 않아 레이 아웃 면적을 감소시킨 것이다.This paper relates to a feedback decoder circuit requiring a pulsed output. Previously, when the address signal input was at a high level, the word line signal was always kept at a high level so that power consumption was unnecessarily increased. ) And a feedback circuit (2) between the MOS transistors (N 1 to N 4 ) so that when the address signal input is at a high level, the word line signal can repeatedly reduce the power consumption by high / low and separate pulses. The layout area is not used because the layout circuit is not used.
Description
제1도는 종래의 디코더 회로도.1 is a conventional decoder circuit diagram.
제2도는 제1도에 따른 출력 파형도.2 is an output waveform diagram according to FIG.
제3도는 본고안의 디코더 회로도.3 is a decoder circuit diagram of the present invention.
제4도는 제3도에 따른 출력 파형도.4 is an output waveform diagram according to FIG.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1:인버터 2:궤환 회로1: inverter 2: feedback circuit
3:딜레이부3: delay
본고안은 IC 메모리 칩내의 디코더 회로에 관한 것으로, 특히 펄스화된 출력을 필요로 하는 궤환형 디코더 회로에 관한 것이다.The present invention relates to a decoder circuit in an IC memory chip, and more particularly to a feedback decoder circuit requiring a pulsed output.
종래의 디코더 회로는 제1도와 같이 어드레스(AØ ~ A3)가 게이트에 입력되는 다수의 모스 트랜지스터(N1~ N4)와, 상기 모스 트랜지스터(N1~ N4)에 병렬 접속된 공핍형 n 채널 트랜지스터(N0)와, 사기 모스 트랜지스터(N1~ N4)와 공핍형 n 채널 트랜지스터(N0)의 공통 접점 출력을 인버팅시키는 피모스 트랜지스터(P0)와 앤모스 트랜지스터(N)로 구성된 인버터(1)를 구비하여 이루어진다.In the conventional decoder circuit, as shown in FIG. 1, a plurality of MOS transistors N 1 to N 4 to which addresses AØ to A 3 are input to a gate and a depletion type connected in parallel to the MOS transistors N 1 to N 4 are shown. n-channel transistors (n 0), and a fraud MOS transistor (n 1 ~ n 4) and a depletion type n PMOS transistor (P 0) and the NMOS transistor for inverting the common contact point output of the channel transistors (n 0) (n It is provided with an inverter (1) consisting of.
이와 같이 구성된 종래의 디코더 회로의 동작을 살펴보면 모든 어드레스 신호(A~A3)들이 하이레벨로 입력될때 노드(A)에서의 레벨은 로우레벨이 되고 인버터(1)를 통하여 하이레벨이 된다(제2도참조).Referring to the operation of the conventional decoder circuit configured as described above, all address signals A When ˜A 3 ) are input at the high level, the level at the node A becomes low level and becomes high level through the inverter 1 (see FIG. 2).
따라서, 종래에는 어드레스 신호 입력이 하이레벨일때 워드라인신호는 항상 하이레벨을 유지하기 때문에 소비전력이 불필요하게 증가되며 별도의 어드레스 트랜지스터 디텍터 회로를 필요로 하는 결점이 있다.Therefore, in the related art, since the word line signal is always maintained at a high level when the address signal input is at a high level, power consumption is unnecessarily increased and a separate address transistor detector circuit is required.
본 고안은 이와같은 종래의 결점을 해결하기 위한 것으로 디코더에서 출력되는 펄스화된 신호를 직접 메모리 셀에 연결하여 메모리 셀의 소비전력을 감소시키며 별도의 펄스화 회로를 사용하지 않는 디코더 회로를 제공하는데 그 목적이 있다.The present invention is to solve the above-mentioned shortcomings, and by connecting the pulsed signal output from the decoder directly to the memory cell to reduce the power consumption of the memory cell and to provide a decoder circuit that does not use a separate pulsed circuit The purpose is.
이하에서 이와같은 목적을 달성하기 위한 본 고안의 실시예를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings.
제3도는 본고안의 회로도로 어드레스 회로가 게이트에 입력되는 다수의 모스 트랜지스터(N1~N4)와 공핍형 n 채널 트랜지스터(N0) 그리고 인버터(1)로 구성되는 회로에 있어서, 상기 모스 트랜지스터(N1~N4)접지측에 p 채널 트랜지스터(p2)를 구비하고 상기 p 채널 트랜지스터(p2)와 인버터(1)의 출력측사이에 인버터(1)의 신호를 일정시간 지연시키는 딜레이부(3)를 구비하여 궤환회로(2)를 구성한 것이다.3 is a circuit diagram of the present invention, in which a MOS transistor (N 1 to N 4 ), a depletion-type n-channel transistor (N 0 ), and an inverter (1) in which an address circuit is input to a gate, is included in the MOS transistor. (N 1 ~ N 4), the delay unit for having a p-channel transistor (p 2) on the ground side, and a predetermined time delay a signal of the inverter (1) between the output side of the p-channel transistor (p 2) and the inverter (1) (3) is provided and the feedback circuit 2 is comprised.
이와같이 구성된 본고안은 어드레스 신호(AØ ~ A3)가 모스 트랜지스터(N1~ N4)에 하이레벨로 입력될 때 노드(A)는 로우레벨이 되고 인버터(1)를 통해 하이레벨이 된다. 이러한 하이레벨은 궤환회로(2)의 딜레이부(3)를 통해 일정시간 지연된 후 p 채널 트랜지스터(p2)를 오프시켜 노드(A)가 하이레벨이 된다.In this configuration configured as described above, when the address signals AØ to A 3 are input to the MOS transistors N 1 to N 4 at a high level, the node A is at a low level and is at a high level through the inverter 1. This high level is delayed for a predetermined time through the delay unit 3 of the feedback circuit 2, and then the p-channel transistor p 2 is turned off so that the node A becomes a high level.
따라서, 입력되는 어드레스 신호가 하이레벨일 경우에 B와 같이 하이/로우를 반복하는 출력을 만들게 된다.Therefore, when the input address signal is at a high level, an output that repeats high / low like B is produced.
이상에서 설명한 바와같은 본고안은 디코더에서 펄스화되어 출력되는 신호를 직접 메모리셀에 연결하여 메모리셀의 소비전력을 감소시킬 수 있으며 별도의 펄스화 회로를 필요로 하지 않기 때문에 칩의 레이아웃 면적을 감소시킬 수 있는 효과가 있다.As described above, the present invention can reduce the power consumption of the memory cell by directly connecting the signal pulsed and outputted from the decoder to the memory cell, and reduces the layout area of the chip because it does not require a separate pulsed circuit. It can be effected.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019910023426U KR0119247Y1 (en) | 1991-12-23 | 1991-12-23 | Decoder circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019910023426U KR0119247Y1 (en) | 1991-12-23 | 1991-12-23 | Decoder circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930015980U KR930015980U (en) | 1993-07-28 |
| KR0119247Y1 true KR0119247Y1 (en) | 1998-08-01 |
Family
ID=19325185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019910023426U KR0119247Y1 (en) | 1991-12-23 | 1991-12-23 | Decoder circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0119247Y1 (en) |
-
1991
- 1991-12-23 KR KR2019910023426U patent/KR0119247Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR930015980U (en) | 1993-07-28 |
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