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KR970067799A - 반도체장치 - Google Patents

반도체장치 Download PDF

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Publication number
KR970067799A
KR970067799A KR1019960037793A KR19960037793A KR970067799A KR 970067799 A KR970067799 A KR 970067799A KR 1019960037793 A KR1019960037793 A KR 1019960037793A KR 19960037793 A KR19960037793 A KR 19960037793A KR 970067799 A KR970067799 A KR 970067799A
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South Korea
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main surface
wiring board
external electrode
semiconductor device
chip
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KR1019960037793A
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English (en)
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KR100194747B1 (ko
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요시히로 토미타
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기타오카 다카시
미쓰비시덴기 주식회사
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Publication of KR970067799A publication Critical patent/KR970067799A/ko
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Publication of KR100194747B1 publication Critical patent/KR100194747B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

반도체칩의 탑재된 반도체장치에 관한 것으로써, 휘어짐이 방지되는 구조를 갖고 소형화되도록 하기 위해 제1 및 제2 주면을 갖고, 그의 제1 또는 제2 주면 상에 여러개의 패드전극이 형성된 반도체칩, 제1 주면 및 제2 주면을 갖고, 제1 주면에 여러개의 칩접속용 패턴이 마련되고 제2 주면에 여러개의 외부 전극부가 마련되는 배선판 및 여러개의 패드전극을 포함하는 반도체칩 전체 및 여러개의 칩접속패턴을 포함하는 배선판의 제1 주면을 피복해서 형성되는 수지를 마련한다. 이것에 의해, 휘어짐을 보다 효과적으로 억제하여, 장치의 신뢰성을 향상할 수 있다.

Description

반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
도 1은 본 발명의 제1 실시예에 따른 반도체장치의 단면도

Claims (12)

  1. 제1 및 제2 주면을 갖고, 그의 상기 제1 또는 제2 주면 상에 여러개의 패드전극이 형성된 반도체칩, 제1 주면 및 제2 주면을 갖고, 상기 제1 주면에 여러개의 칩접속용 패턴이 마련되고 제2 주면에 여러개의 외부전극부가 마련되는 배선판 및 상기 여러개의 패드 전극을 포함하는 상기 반도체칩 전체 및 상기 여러개의 칩접속 패턴을 포함하는 상기 배선판의 제1 주면을 피복해서 형성되는 수지를 포함하고, 상기 반도체칩은 상기 배선판의 제1 주면을 도포하고, 상기 여러개의 칩접속용 패턴은 상기 여러개의 외부전극부 중 대응하는 외부전극부에 전기적으로 접속되고, 각각 상기 여러개의 패드전극중 대용하는 패드전극에 전기적으로 접속되며, 상기 여러개의 외부전극부가 형성되는 영역은 상기 여러개의 칩접속패턴이 형성되는 영역 보다 작은 반도체장치.
  2. 제1항에 있어서, 상기 열거개의 패드전극은 상기 반도체칩의 제2주면 상에 형성되고, 상기 여러개의 패드전극 중 대응하는 패드전극에 각각 직접 접속된 여러개의 접속전극, 상기 여러개의 접속전극 중 대응하는 접속전극에 각각 직접 접속되는 상기 여러개의 칩접속패턴 및 상기 여러개의 접속전극을 포함하는 상기 배선판의 제1 주면을 피복하여 형성된 수지를 더 포함하는 반도체장치.
  3. 제1항에 있어서, 여러개의 패드전극은 상기 반도체칩의 제1 주면 상에 형성되고, 상기 여러개의 칩접속패턴은 상기 반도체칩을 둘러싸고,금속선에 의해 상기 여러개의 패드전극 중 대응하는 패드전극에 각각 접속되는 반도체장치.
  4. 제3항에 있어서, 상기 반도체칩은 상기 배선판에 배치되어 접합되는 반도체장치.
  5. 제2항에 있어서, 상기 수지는 트랜스퍼 성형법에 의해 형성되는 반도체장치.
  6. 제5항에 있어서, 상기 배선판의단부에서 상기 여러개의 칩접속패턴이 형성되는 영역까지의 거리는 상기 배선판의 단부에서 상기 여러개의 외부전극부가 형성되는 영역까지의 거리보다 작고, 상기 수지는 상기 배선판의 측면 및 상기 여러개의 외부전극부가 형성되는 부분을 제외하고 상기 배선판의 상기 주면의 일부를 도포하는 반도체장치.
  7. 제6항에 있어서, 상기 여러개의 외부전극부의 각각은 상기 배선판의 상기 제2주면에 직접 접속된 도통패턴 및 상기 도통패턴에 직접 접속된 거의 구형의 외부전극을 포함하는 반도체장치.
  8. 제6항에 있어서, 상기 여러개의 외부전극부의 각각은 가지형(branchlike) 접속핀을 포함하는 반도체장치.
  9. 제3항에 있어서, 상기 수지는 트랜스퍼 성형법에 의해 형성되는 반도체장치.
  10. 제9항에 있어서, 상기 배선기판의 단부에서 상기 여러개의 칩접속패턴이 형성되는 영역까지의 거리가 상기 배선판의 단부에서 상기 여러개의 외부전극부가 형성되는 영역까지의 거리 보다 작고, 상기 수지는 상기 배선판의 측면 및 상기 여러개의 외부전극부가 형성되는 부분을 제외하고 상기 배선판의 제2 주면의 일부를 피복하는 반도체장치.
  11. 제10항에 있어서, 상기 여러개의 외부전극부는 상기 배선판의 제2 주면에 직접 접속되는 도통패턴 및 상기 도통패턴에 직접 접속되는 거의 구형의 외부전극을 포함하는 반도체장치.
  12. 제10항에 있어서, 상기 여러개의 외부전극부의 각각은 가지형 접속핀을 포함하는 반도체장치.
KR1019960037793A 1996-03-27 1996-09-02 반도체장치 KR100194747B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7204396A JPH09260436A (ja) 1996-03-27 1996-03-27 半導体装置
JP96-072043 1996-03-27

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KR970067799A true KR970067799A (ko) 1997-10-13
KR100194747B1 KR100194747B1 (ko) 1999-06-15

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US (1) US5708304A (ko)
JP (1) JPH09260436A (ko)
KR (1) KR100194747B1 (ko)
CN (1) CN1099710C (ko)
DE (1) DE19651122C2 (ko)

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US5888850A (en) * 1997-09-29 1999-03-30 International Business Machines Corporation Method for providing a protective coating and electronic package utilizing same
US6448665B1 (en) 1997-10-15 2002-09-10 Kabushiki Kaisha Toshiba Semiconductor package and manufacturing method thereof
US6038136A (en) * 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
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US5708304A (en) 1998-01-13
JPH09260436A (ja) 1997-10-03
CN1099710C (zh) 2003-01-22

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