[go: up one dir, main page]

KR970053968A - ESD Protection Structure of Semiconductor Device with Multiple Power Supplies - Google Patents

ESD Protection Structure of Semiconductor Device with Multiple Power Supplies Download PDF

Info

Publication number
KR970053968A
KR970053968A KR1019950066987A KR19950066987A KR970053968A KR 970053968 A KR970053968 A KR 970053968A KR 1019950066987 A KR1019950066987 A KR 1019950066987A KR 19950066987 A KR19950066987 A KR 19950066987A KR 970053968 A KR970053968 A KR 970053968A
Authority
KR
South Korea
Prior art keywords
power supplies
semiconductor device
esd protection
protection structure
multiple power
Prior art date
Application number
KR1019950066987A
Other languages
Korean (ko)
Inventor
성영섭
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950066987A priority Critical patent/KR970053968A/en
Publication of KR970053968A publication Critical patent/KR970053968A/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

복수개의 전원을 갖는 반도체장치의 ESD 방지구조가 포함되어 있다. 본 발명에 따른 복수개(N개)의 전원을 갖는 반도체장치의 ESD 방지구조는, 상기 N개의 모든 전원 사이에 각각 한 개씩의 프로텍션 다이오드가 접속되며, N(N-1)/2 (N〉2) 만클의 프로텍션 다이오드를 포함하는 ESD 방지수단을 구비하는 것을 특징으로 한다. 따라서 본 발명은 상기 N개의 모든 전원 사이에 프로텍션 다이오드를 접속함으로써 가익 각 전원사이에 발생할 수 있는 ESD를 최대한 방지할 수 있다.An ESD protection structure of a semiconductor device having a plurality of power sources is included. In the ESD protection structure of a semiconductor device having a plurality of (N) power supplies according to the present invention, one protection diode is connected between all of the N power supplies, and N (N-1) / 2 (N> 2). ) ESD protection means including a protection diode of manckle. Therefore, the present invention can prevent the ESD that can occur between each power source by connecting a protection diode between all the N power supplies.

Description

복수개의 전원을 갖는 반도체장치의 ESD 방지구조ESD Protection Structure of Semiconductor Device with Multiple Power Supplies

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 복수개의 전원을 갖는 반도체장치의 ESD 방지구조를 나타내는 도면이다.1 is a diagram showing an ESD protection structure of a semiconductor device having a plurality of power sources according to the present invention.

Claims (1)

복수개(N개)의 전원을 갖는 반도체장치의 ESD 방지구조에 있어서, 상기 N개의 모든 전원 사이에 각각 한 개씩의 프로텍션 다이오드가 접속되며, N(N-1)/2(N〉2)만큼의 프로텍션 다이오드를 포함하는 ESD방지수단을 구비하는ㄱ 설을 특징으로 하는 복수개의 전원을 갖는 반도체장치의 ESD 방지구조.In the ESD protection structure of a semiconductor device having a plurality of (N) power supplies, one protection diode is connected between all of the N power supplies, and each N (N-1) / 2 (N> 2) An ESD protection structure of a semiconductor device having a plurality of power supplies, characterized by comprising a ESD protection means including a protection diode. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950066987A 1995-12-29 1995-12-29 ESD Protection Structure of Semiconductor Device with Multiple Power Supplies KR970053968A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950066987A KR970053968A (en) 1995-12-29 1995-12-29 ESD Protection Structure of Semiconductor Device with Multiple Power Supplies

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950066987A KR970053968A (en) 1995-12-29 1995-12-29 ESD Protection Structure of Semiconductor Device with Multiple Power Supplies

Publications (1)

Publication Number Publication Date
KR970053968A true KR970053968A (en) 1997-07-31

Family

ID=66637265

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950066987A KR970053968A (en) 1995-12-29 1995-12-29 ESD Protection Structure of Semiconductor Device with Multiple Power Supplies

Country Status (1)

Country Link
KR (1) KR970053968A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100861193B1 (en) * 2002-07-18 2008-09-30 주식회사 하이닉스반도체 Electrostatic discharge protection circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100861193B1 (en) * 2002-07-18 2008-09-30 주식회사 하이닉스반도체 Electrostatic discharge protection circuit

Similar Documents

Publication Publication Date Title
KR910015119A (en) Switching circuit
KR920001541A (en) Semiconductor integrated circuit device
KR940010463A (en) Charge pumps operate on low voltage power supplies
KR970049453A (en) Static and Dynamic Full Adder with N-MOS
DE69411709D1 (en) MICROPARTICLE SWITCHING DEVICE
KR920003635A (en) Active filter device
AR022486A1 (en) METHOD AND PROVISION TO PROVIDE INTEGRATED INTERACTIVE ACCESS TO AT LEAST A BUSINESS FUNCTIONALITY FOR A USER
KR970063275A (en) Semiconductor Integrated Circuits and Circuit Devices Using the Same
KR840006871A (en) Display
KR920009015A (en) Protection circuit of semiconductor chip
KR970053968A (en) ESD Protection Structure of Semiconductor Device with Multiple Power Supplies
KR880001131A (en) Output buffer circuit
KR960026991A (en) Optical coupling element
KR920005456A (en) Broadband amplification circuit
KR910010705A (en) Semiconductor integrated circuit
KR930016096A (en) Composition for promoting wound healing
KR920007509A (en) Thin memory module
KR920003659A (en) Low Noise Output Buffer Circuit
KR970011961A (en) Pad device connecting main pad and dummy pad
KR920008916A (en) Semiconductor heating element
KR970024473A (en) Multiple power system
KR970023389A (en) Semiconductor memory cell placement method
KR910013528A (en) Design method of power and ground metal wiring
KR910008870A (en) Protection circuit of semiconductor chip
KR970058387A (en) Static electricity protection circuit

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19951229

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid