[go: up one dir, main page]

KR970053379A - Method of forming device isolation region - Google Patents

Method of forming device isolation region Download PDF

Info

Publication number
KR970053379A
KR970053379A KR1019950047964A KR19950047964A KR970053379A KR 970053379 A KR970053379 A KR 970053379A KR 1019950047964 A KR1019950047964 A KR 1019950047964A KR 19950047964 A KR19950047964 A KR 19950047964A KR 970053379 A KR970053379 A KR 970053379A
Authority
KR
South Korea
Prior art keywords
oxide film
forming
substrate
isolation region
device isolation
Prior art date
Application number
KR1019950047964A
Other languages
Korean (ko)
Other versions
KR100196420B1 (en
Inventor
구본영
김형진
임현우
정병홍
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950047964A priority Critical patent/KR100196420B1/en
Publication of KR970053379A publication Critical patent/KR970053379A/en
Application granted granted Critical
Publication of KR100196420B1 publication Critical patent/KR100196420B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 기판을 건식 식각하므로써 형성하는 트렌치에서 누설전류가 발생하는 무제점을 해결하기 위한 것으로서, 기판내에 형성된 트렌치상에 산화막을 목표치의 70%~90%의 두께로 형성한 후, 질소나 수소 가스를 포함하는 가스 분위기에서 열처리 공정을 통하여 나머지 산화막을 형성하므로써, 트렌치를 형성하면서 발생한 식각 손상을 보완하며, 이에 따라 반도체 소자의 동작시 누설전류를 방지하고, 리프레쉬 특성을 개선하므로써, 반도체 소자의 품질을 향상시키고, 반도체 제조 공정의 안정화를 기하게 된다.The present invention is to solve the problem that the leakage current occurs in the trench formed by dry etching the substrate, after forming an oxide film on the trench formed in the substrate to a thickness of 70% to 90% of the target value, the nitrogen or hydrogen By forming the remaining oxide film through a heat treatment process in a gas atmosphere containing gas, the etching damage caused by forming the trench is compensated for, thereby preventing leakage current during operation of the semiconductor device and improving refresh characteristics. The quality is improved and the semiconductor manufacturing process is stabilized.

Description

소자 격리 영역의 형성방법Method of forming device isolation region

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2E도는 본 발명의 실시예에 따른 소자 격리 영역의 공정도.2A-2E are process diagrams of device isolation regions in accordance with embodiments of the present invention.

Claims (6)

실리콘 기판(21)상에 산화막(22), 질화막(23), 고온 산화막(24)을 차례로 형성하는 공정과, 상기 고온 산화막(24), 질화막(22)을 패터닝하는 공정과, 상기 고온 산화막(24)을 마스크로 하여 노출된 기판(21)의 일부를 건식식각하여 기판(21)내에 트렌치(25)를 형성하는 공정과, 산화 공정을 실시하여 트렌치(25) 표면상에 산화막(26)을 형성함과 동시에 질소 성분 또는 수소 성분을 기판(21)과 산화막(26)의 계면에 축적시켜 주는 공정과, 상기 기판(21)상에 절연막(28)을 형성하는 공정과, 상기 절연막(28)을 상기 질화막(23)의 상부까지 식각하는 공정과, 남아 있는 질화막(23)과 산화막(22)을 차례로 제거하여, 반도체 소자간의 소자격리 영역(28a)으로 형성하는 공정을 포함하는 것을 특징으로 하는 소자 격리 영역의 형성방법.A step of sequentially forming an oxide film 22, a nitride film 23, and a high temperature oxide film 24 on the silicon substrate 21, a step of patterning the high temperature oxide film 24 and the nitride film 22, and the high temperature oxide film ( A portion of the exposed substrate 21 is dry-etched using the mask 24 as a mask to form the trench 25 in the substrate 21, and an oxidation process is performed to form the oxide film 26 on the trench 25 surface. Forming a nitrogen component or a hydrogen component at the interface between the substrate 21 and the oxide film 26, forming the insulating film 28 on the substrate 21, and forming the insulating film 28. Etching to the upper portion of the nitride film 23, and removing the remaining nitride film 23 and the oxide film 22 in order to form a device isolation region 28a between the semiconductor elements Method for forming device isolation region. 제1항에 있어서, 산화 공정은 일반적인 산화법으로 원하는 두께의 산화막(26)을 성장시키고, N2가스 분위기에서 후속의 열처리 공정을 실시하여 질소 성분을 기판(21)과 산화막(26)의 계면(27)에 축적시키는 것을 특징으로 하는 소자 격리 영역의 형성방법.2. The oxidation process according to claim 1, wherein the oxidation process is performed by growing an oxide film 26 having a desired thickness by a general oxidation method and performing a subsequent heat treatment process in an N 2 gas atmosphere. 27) a method for forming a device isolation region. 제2항에 있어서, H2가스 분의기에서 후속의 열처리 공정을 실시하여 수소 성분을 기판(21)과 산화막(26)의 계면(27)에 축적시키는 것을 특징으로 하는 소자 격리 영역의 형성방법.The method of forming a device isolation region according to claim 2, wherein a hydrogen component is accumulated at an interface 27 between the substrate 21 and the oxide film 26 by performing a subsequent heat treatment step in a H 2 gas separator. . 제1항에 있어서, 산화 공정은 일반적인 산화법으로 원하는 두께의 70%~90% 정도로 성장시키고, N2O가스 분위기에서 후속이 열처리 공정을 실시하여 원하는 두께의 산화막(26)을 형성함과 동시에 질소 성분을 상기 기판(21)과 산화막(26)의 계면(27)에 축적하는 것을 특징으로 하는 소자 격리 영역의 형성방법.2. The oxidation process according to claim 1, wherein the oxidation process is grown to about 70% to 90% of the desired thickness by a general oxidation method, followed by subsequent heat treatment in an N 2 O gas atmosphere to form an oxide film 26 having a desired thickness and nitrogen. A component is accumulated at the interface (27) of the substrate (21) and the oxide film (26). 제4항에 있어서, 상기 후속 처리 공정의 온도는 800℃~1100℃인 것을 특징으로 하는 소자 격리 영역의 형성방법.The method of claim 4, wherein the temperature of the subsequent processing step is between 800 ° C. and 1100 ° C. 6. 제4항에 있어서, 상화 공정시 N2O 가스 대신에 질소 성분을 포함하는 가스 분위기에서 진행되는 것을 특징으로 하는 소자 격리 영역의 형성방법.5. The method of claim 4, wherein the device isolation region is formed in a gas atmosphere containing a nitrogen component instead of the N 2 O gas in the phase of the normalization process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950047964A 1995-12-08 1995-12-08 Method for forimg isolation region in semiconductor device KR100196420B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950047964A KR100196420B1 (en) 1995-12-08 1995-12-08 Method for forimg isolation region in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950047964A KR100196420B1 (en) 1995-12-08 1995-12-08 Method for forimg isolation region in semiconductor device

Publications (2)

Publication Number Publication Date
KR970053379A true KR970053379A (en) 1997-07-31
KR100196420B1 KR100196420B1 (en) 1999-06-15

Family

ID=19438725

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950047964A KR100196420B1 (en) 1995-12-08 1995-12-08 Method for forimg isolation region in semiconductor device

Country Status (1)

Country Link
KR (1) KR100196420B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100333714B1 (en) * 1998-06-29 2002-08-22 주식회사 하이닉스반도체 Method for forming isolation layer in semiconductor device
KR100468692B1 (en) * 1997-09-22 2005-03-16 삼성전자주식회사 Method for forming isolation film having trench type to isolate devices

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100444609B1 (en) * 2002-10-30 2004-08-16 주식회사 하이닉스반도체 Method of forming an isolation layer in a semiconductor device
KR100854877B1 (en) * 2006-12-27 2008-08-28 주식회사 하이닉스반도체 Metal wiring formation method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100468692B1 (en) * 1997-09-22 2005-03-16 삼성전자주식회사 Method for forming isolation film having trench type to isolate devices
KR100333714B1 (en) * 1998-06-29 2002-08-22 주식회사 하이닉스반도체 Method for forming isolation layer in semiconductor device

Also Published As

Publication number Publication date
KR100196420B1 (en) 1999-06-15

Similar Documents

Publication Publication Date Title
KR970003794A (en) Device Separation Method of Semiconductor Device
KR100273281B1 (en) Method of forming insulator film of semiconductor device
KR970013198A (en) Device isolation insulating film formation method of semiconductor device
US6624090B1 (en) Method of forming plasma nitrided gate dielectric layers
KR970053379A (en) Method of forming device isolation region
KR970030626A (en) Device Separation Method of Semiconductor Device
KR100405015B1 (en) A method of manufacturing semiconductor device
US6624095B1 (en) Method for manufacturing a semiconductor device
JPS5812732B2 (en) Manufacturing method for semiconductor devices
JPH07176742A (en) Manufacture of semiconductor device and semiconductor device
KR0138125B1 (en) Gate dielectric film formation method of transistor
KR100282425B1 (en) Method for fabricating of capacitor
KR970013189A (en) Device isolation method of semiconductor integrated circuit
KR0167239B1 (en) Method of Manufacturing Separator for Semiconductor Device
JPH0374842A (en) Manufacture of semiconductor device
KR970008478A (en) Device Separator Formation Method
KR940002966A (en) Method of removing interlayer short circuit by polysilicon etching residue
JPH05335408A (en) Forming method of element isolation region
KR970003808A (en) Device separator manufacturing method
KR950021102A (en) Metal wiring formation method of semiconductor device
JPH03153045A (en) Manufacture of semiconductor device
KR970003710A (en) Semiconductor device manufacturing method
KR980005359A (en) Manufacturing method of semiconductor device
JPH0494567A (en) Manufacturing method of semiconductor device
KR980003820A (en) Method for forming polysilicon layer pattern of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19951208

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19951208

Comment text: Request for Examination of Application

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19980828

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19981228

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19990220

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19990222

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20020107

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20030107

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20040107

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20050110

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20060105

Start annual number: 8

End annual number: 8

FPAY Annual fee payment

Payment date: 20070125

Year of fee payment: 9

PR1001 Payment of annual fee

Payment date: 20070125

Start annual number: 9

End annual number: 9

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

Termination category: Default of registration fee

Termination date: 20090110