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KR0138125B1 - Gate dielectric film formation method of transistor - Google Patents

Gate dielectric film formation method of transistor

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Publication number
KR0138125B1
KR0138125B1 KR1019940012750A KR19940012750A KR0138125B1 KR 0138125 B1 KR0138125 B1 KR 0138125B1 KR 1019940012750 A KR1019940012750 A KR 1019940012750A KR 19940012750 A KR19940012750 A KR 19940012750A KR 0138125 B1 KR0138125 B1 KR 0138125B1
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South Korea
Prior art keywords
oxide film
dielectric film
gate dielectric
forming
transistor
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KR1019940012750A
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Korean (ko)
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KR960002634A (en
Inventor
신승우
최재성
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김주용
현대전자산업주식회사
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Priority to KR1019940012750A priority Critical patent/KR0138125B1/en
Publication of KR960002634A publication Critical patent/KR960002634A/en
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Publication of KR0138125B1 publication Critical patent/KR0138125B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN

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  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도에 소자 제조공정 중 트랜지스터의 게이트 유전막 형성방법에 관한 것으로, 반도체기판(1)에 700내지 900℃에서 산화막(2)을 형성하는 단계; 800내지 1000℃에서 NH3, O2 개스를 주입시켜 질화성산화막(3)을 형성함으로써 본 발명은 종래 공정 조건(온도)을 유지하면서도 종래 공정 방법에 의해 형성한 단층 산화막에 비해 유전 강도가 증가하고 누설전류를 줄이면서 후단 공정에 의한 유전막의 손상을 줄일수 있으므로 현재의 게이트용 유전막의 두께보다 더 감소 시키면서도 동등하거나 더 뛰어난 유전막 특성을 얻을 수 있다.The present invention relates to a method of forming a gate dielectric film of a transistor in a device manufacturing process on a peninsula, comprising: forming an oxide film (2) at 700 to 900 ° C on a semiconductor substrate (1); By forming NH3 and O2 gas at 800 to 1000 ° C to form the nitride oxide film 3, the present invention maintains the conventional process conditions (temperature) while increasing the dielectric strength and leakage compared to the single layer oxide film formed by the conventional process method. By reducing the current and reducing the damage of the dielectric film by the post-stage process, it is possible to obtain the same or better dielectric film properties while reducing the current thickness of the gate dielectric film.

Description

트랜지스터의 게이트 유전막 형성 방법Gate dielectric film formation method of transistor

제1a도 내지 제1c도는 본 발명의 일실시예에 따른 게이트 유전막 형성 공정 단면도.1A to 1C are cross-sectional views of a gate dielectric film forming process according to an embodiment of the present invention.

*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1:반도체 기판2:산화막1: Semiconductor Substrate 2: Oxide Film

3:질화산화막3: nitride oxide film

본 발명은 반도체 장치 제조 방법에 관한 것으로, 특히 트랜지스터의 게이트 유전막 형성 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a gate dielectric film of a transistor.

종래 트랜지스터의 게이트 유전막으로는 열공정으로 형성시킨 산화막을 사용한다. 반도체 소자가 고집적화 되어감에 따라 트랜지스터의 게이트 유전막의 두께도 줄어들게 되면서 열공정으로 형성한 산화막을 트랜지스터의 게이트 유전막으로 사용하는데는 다음과 같은 문제점을 초래하게 되었다.An oxide film formed by a thermal process is used as a gate dielectric film of a conventional transistor. As semiconductor devices have been highly integrated, the thickness of the gate dielectric film of the transistor is also reduced, resulting in the following problems in using the oxide film formed by the thermal process as the gate dielectric film of the transistor.

첫째, 산화막을 통한 누설전류 값이 증가하고 유전 강도는 약해지게 되어 게이트 유전막의 필수 구비 조건인 절연체(insulator)로서의 성능이 약화된다.First, the leakage current value through the oxide film is increased and the dielectric strength is weakened, so that the performance as an insulator, which is an essential condition of the gate dielectric film, is weakened.

둘째, 게이트 전극 형성을 위한 식각 공정시 사용하는 플라즈마로 인하여 산화막이 손상된다. 또한, 게이트 전극을 폴리실리콘막으로 형성하는 경우 폴리실리콘막에 이온주입되는 불순물이 산화막으로 침투하여 게이트 유전막의 특성을 저하시킨다.Second, the oxide film is damaged by the plasma used in the etching process for forming the gate electrode. In addition, when the gate electrode is formed of a polysilicon film, impurities implanted into the polysilicon film penetrate into the oxide film to deteriorate the characteristics of the gate dielectric film.

상기와 같은 단점을 보완하고자, 게이트 유전막을 형성하는 다른 종래 기술은 800℃에서 산화막을 형성한 후 900℃에서 N2 가스 분위기를 거쳐 산화막 상태를 좀더 조밀하게 하여 유전 특성을 향상시키는 방법을 사용하고 있으나, 단층의 산화막 구조는 그대로 유지하고 있어 상기 언급된 산화막의 단점은 그대로 내포하고 있다.In order to make up for the above disadvantages, another conventional technique of forming a gate dielectric layer uses a method of forming an oxide layer at 800 ° C. and then densifying the oxide state more closely through an N 2 gas atmosphere at 900 ° C. to improve dielectric properties. The monolayer oxide structure is maintained as it is, and the disadvantages of the oxide layer mentioned above are intact.

따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은의 유전 강도가 뛰어나고, 누설전류 정도가 적으며, 플라즈마 분위기에서의 유전막 손상 정도를 줄일 수 있으며, 이온주입시 불순물 침투에 저항력이 강한 게이트 유전막 형성 방법을 제공하는데 그 목적이 있다.Therefore, the present invention devised to solve the above problems is excellent gate dielectric strength, low leakage current degree, can reduce the dielectric film damage in the plasma atmosphere, strong gate resistance to impurity penetration during ion implantation The object is to provide a method for forming a dielectric film.

상기 목적을 달성하기 위하여 본 발명은 트랜지스터의 게이트 유전막 형성 방법에 있어서, 반도체 기판 상에 산화막을 형성하는 단계; 상기 산화막을 NH3 및 O2 가스와 반응시켜, 상기 산화막의 상부 표면과 상기 반도체 기판과 상기 산화막의 계면에 각각 질화산화막을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method of forming a gate dielectric film of a transistor, comprising: forming an oxide film on a semiconductor substrate; And reacting the oxide film with NH 3 and O 2 gas to form a nitride oxide film on the upper surface of the oxide film and the interface between the semiconductor substrate and the oxide film, respectively.

이하, 첨부된 도면 제1A도 내지 제1C도를 참조하여 본 발명의 일실시예를 상술한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1C.

본 발명에서는 트랜지스터의 게이트 유전막으로 사용되는 산화막의 단점을 보완하고자 산화막에 비해 유전 강도가 뛰어나고, 누설전류 정도가 적으면서 플라즈마분위기 에서의 유전막 손상이나, 이온주입시 불순물 침투에 저항력이 강한 질화막 계통의 층을 추가하는 것을 그 원리로 한다.In the present invention, in order to compensate for the shortcomings of the oxide film used as the gate dielectric film of the transistor, the dielectric strength of the nitride film is superior to that of the oxide film, and the leakage current is low and the resistance of the dielectric film damage in the plasma atmosphere or the impurity penetration during ion implantation is reduced. The principle is to add layers.

본 발명의 일실시예에 따른 트랜지스터의 게이트 형성 방법은 다음과 같이 이루어진다.A gate forming method of a transistor according to an embodiment of the present invention is performed as follows.

먼제 제1A도에 도시한 바와 같이 반도체 기판(1) 상에 산화막(2)을 700℃ 내지 900℃ 온도에서 형성한다. 상기 산화막 형성 온도는 종래의 게이트 유전막인 산화막 형성 온도와 동일한 온도이다.As shown in FIG. 1A, the oxide film 2 is formed on the semiconductor substrate 1 at a temperature of 700 ° C to 900 ° C. The oxide film formation temperature is the same temperature as the oxide film formation temperature which is a conventional gate dielectric film.

다음으로, 제1B도에 도시한 바와 같이, 기판 온도가 800℃ 내지 1000℃인 온도 조건에서 NH3 및 O2 가스를 챔버 내에 주입시켜 상기 산화막(2)과 반응되도록 한다.Next, as shown in FIG. 1B, NH3 and O2 gas are injected into the chamber at a temperature of 800 ° C to 1000 ° C so as to react with the oxide film 2.

이때, 주입되는 NH3 및 O2 가스는 기판 온도가 780℃ 이상일 때 다음과 같은 반응을 한다.In this case, the injected NH 3 and O 2 gases react as follows when the substrate temperature is 780 ° C. or more.

반응식( 4NH3+ 3O2→ 2N2+ 6H2O)Scheme (4NH 3 + 3O 2 → 2N 2 + 6H 2 O)

따라서, 기판 온도가 800℃ 내지 1000℃인 조건에서 NH3및 O2가스는 불안정한 N2, H2O 종(種)이 되면서, 제1C도에 도시한 바와 같이 상기 산화막(2)과 반응하여 산화막 위에 질화산화막(oxynitride, SiaObNcHz, 3)을 형성하게 되는데, 산화막 위에 질화산화막이 형성되는 동안 NH3가스가 산화막 내부로 확산 및 열분해되고, 상기 반도체 기판(1)과 상기 산화막(2) 계면에 존재하는 결함(defect) 등을 질소가 포획(trap)하면서 상기 산화막 아래에 질화산화막(3)이 형성된다. 따라서, 산화막 아래에는 산화막 위 보다 질화산화막이 얇게 형성된다.Therefore, NH 3 and O 2 gas becomes unstable N 2 , H 2 O species under the condition that the substrate temperature is 800 ° C. to 1000 ° C., and reacts with the oxide film 2 as shown in FIG. 1C. An oxide film (oxynitride, Si a O b N c Hz, 3) is formed on the oxide film. During the formation of the nitride oxide film on the oxide film, NH 3 gas is diffused and thermally decomposed into the oxide film, and the semiconductor substrate 1 and the Nitride oxide film 3 is formed under the oxide film while nitrogen traps defects or the like present at the interface of oxide film 2. Therefore, the nitride oxide film is formed thinner below the oxide film than on the oxide film.

상기와 같이 이루어지는 본 발명은, 단층 산화막에 비해 유전 강도가 증가하고 누설전류가 감소된다. 또한, 식각 공정 및 이온주입 공정에서 발생하는 유전막의 특성 저하를 방지할 수 있다.In the present invention as described above, the dielectric strength is increased and the leakage current is reduced as compared with the single layer oxide film. In addition, it is possible to prevent deterioration of characteristics of the dielectric film generated in the etching process and the ion implantation process.

Claims (3)

트랜지스터의 게이트 유전막 형성 방법에 있어서, 반도체 기판 상에 산화막을 형성하는 단계; 상기 산화막을 NH3및 O2가스와 반응시켜, 상기 산화막의 상부 표면과 상기 반도체 기판과 상기 산화막의 계면에 각각 질화산화막을 형성하는 단계를 포함하여 이루어지는 트랜지스터의 게이트 유전막 형성 방법.A method of forming a gate dielectric film of a transistor, comprising: forming an oxide film on a semiconductor substrate; Reacting the oxide film with NH 3 and O 2 gas to form a nitride oxide film on an upper surface of the oxide film and an interface between the semiconductor substrate and the oxide film, respectively. 제1항에 있어서, 상기 산화막을 700℃ 내지 900℃의 기판 온도 조건에서 형성하는 트랜지스터의 게이트 유전막 형성 방법.The method of claim 1, wherein the oxide film is formed at a substrate temperature of 700 ° C. to 900 ° C. 7. 제1항 또는 제2항에 있어서, NH3및 O2가스를 800℃ 내지 1000℃의 기판 온도 조건에서 상기 산화막과 반응시키는 트랜지스터의 게이트 유전막 형성 방법.The method of forming a gate dielectric film of a transistor according to claim 1 or 2, wherein NH 3 and O 2 gases are reacted with the oxide film at a substrate temperature of 800 ° C to 1000 ° C.
KR1019940012750A 1994-06-07 1994-06-07 Gate dielectric film formation method of transistor KR0138125B1 (en)

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KR0138125B1 true KR0138125B1 (en) 1998-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100428876B1 (en) * 1996-12-20 2004-07-27 주식회사 하이닉스반도체 Manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100428876B1 (en) * 1996-12-20 2004-07-27 주식회사 하이닉스반도체 Manufacturing method of semiconductor device

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