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KR970051096A - Multistage Charge Pump Circuit - Google Patents

Multistage Charge Pump Circuit Download PDF

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Publication number
KR970051096A
KR970051096A KR1019950065660A KR19950065660A KR970051096A KR 970051096 A KR970051096 A KR 970051096A KR 1019950065660 A KR1019950065660 A KR 1019950065660A KR 19950065660 A KR19950065660 A KR 19950065660A KR 970051096 A KR970051096 A KR 970051096A
Authority
KR
South Korea
Prior art keywords
charge pump
pump circuit
pumping
stage
series
Prior art date
Application number
KR1019950065660A
Other languages
Korean (ko)
Inventor
하창완
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950065660A priority Critical patent/KR970051096A/en
Publication of KR970051096A publication Critical patent/KR970051096A/en

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  • Read Only Memory (AREA)

Abstract

본 발명은 다단계 챠지펌프 회로에 관한 것으로서, 단계별로 펌프 회로를 병렬로 연결하여 펌핑이 각 전압레벨에 맞게 최적화 되어 펌핑되므로써 펌핑 상승시간을 최대한으로 줄일 수 있어 플래쉬 메모리셀의 프로그램 시간등을 감소시킬 수 있도록 한 다단계 챠지펌프 회로에 관한 것이다.The present invention relates to a multi-stage charge pump circuit, and by connecting the pump circuits in parallel in stages, the pumping is optimized for each voltage level, so that the pumping rise time can be reduced to the maximum, thereby reducing the program time of the flash memory cell. To a multi-stage charge pump circuit.

Description

다단계 챠지펌프 회로Multistage Charge Pump Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 2 도는 본 발명에 따른 다단계 챠지펌프 회로도.2 is a multi-stage charge pump circuit in accordance with the present invention.

제 3 도는 종래 및 본 발명에 따른 다단계 챠지펌프 회로의 출력을 비교하기 위한 파형도.3 is a waveform diagram for comparing the output of the multistage charge pump circuit according to the prior art and the present invention.

Claims (2)

제1 및 제2클럭신호 각각의 입력에 따라 펌핑전압을 출력하도록 구성되는 챠지펌프 회로에 있어서, 각각의 펌프노드에 일정전압을 유지시켜주기 위한 다수의 소오싱 트랜지스터, 클럭신호에 따라 턴온/턴오프 되어 전하를 전달해 주는 다수의 전달 트랜지스터 및 결합 캐패시터로 각각 구성되는 펌핑 유니트들이 직렬 구조로 접속되는 제1챠지펌프 회로와, 상기 제1챠지펌프 회로의 구성과 동일한 다수의 펌핑 유니트들이 직렬구조로 접속되는 제2챠지펌프 회로와, 펌프노드에 일정전압을 유지시켜주기 위한 소오싱 트랜지스터, 입력신호에 따라 턴온/턴오프 되어 전하를 전달해 주는 전달 트랜지스터 및 결합 캐패시터로 각각 구성되는 펌핑 유니트들이 직렬구조로 접속되는 제3챠지펌프 회로가 병렬로 접속되는 것을 특징으로 하는 다단계 챠지펌프 회로.In a charge pump circuit configured to output a pumping voltage according to an input of a first clock signal and a second clock signal, a plurality of sourcing transistors for maintaining a constant voltage at each pump node, and a turn-on / turn according to a clock signal. A first charge pump circuit in which pumping units each composed of a plurality of transfer transistors and coupling capacitors, which are turned off to transfer charges, is connected in series, and a plurality of pumping units having the same configuration as the first charge pump circuit are connected in series. A series of pumping units, each composed of a second charge pump circuit connected to each other, a sourcing transistor for maintaining a constant voltage at the pump node, a transfer transistor for transferring charge by turning on / off according to an input signal, and a coupling capacitor Multi-stage charge pump circuit characterized in that the third charge pump circuit is connected in parallel in. 제 1 항에 있어서, 상기 고정된 단수인 2m스테이지의 챠지펌프 회로에 부가하여 2m-2, 2m-4, ..., 2스테이지로 구성된 챠지펌프 회로가 병렬로 추가되서 펌핑효율을 개선시킬 수 있도록 구성된 것을 특징으로 하는 다단계 챠지펌프 회로.According to claim 1, In addition to the fixed stage of the charge pump circuit of the 2m stage charge pump circuit consisting of 2m-2, 2m-4, ..., two stages can be added in parallel to improve the pumping efficiency Multi-stage charge pump circuit, characterized in that configured to. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065660A 1995-12-29 1995-12-29 Multistage Charge Pump Circuit KR970051096A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950065660A KR970051096A (en) 1995-12-29 1995-12-29 Multistage Charge Pump Circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950065660A KR970051096A (en) 1995-12-29 1995-12-29 Multistage Charge Pump Circuit

Publications (1)

Publication Number Publication Date
KR970051096A true KR970051096A (en) 1997-07-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950065660A KR970051096A (en) 1995-12-29 1995-12-29 Multistage Charge Pump Circuit

Country Status (1)

Country Link
KR (1) KR970051096A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100674961B1 (en) * 2005-02-26 2007-01-26 삼성전자주식회사 Step-up voltage generation circuit having an additional pump circuit and a step-up voltage generation method thereof
US7224616B2 (en) 2004-11-15 2007-05-29 Samsung Electronics Co., Ltd. Circuit and method for generating wordline voltage in nonvolatile semiconductor memory device
KR100740953B1 (en) * 2000-07-03 2007-07-19 가부시키가이샤 히타치세이사쿠쇼 Semiconductor integrated circuit and nonvolatile semiconductor memory
KR100911373B1 (en) * 2008-04-22 2009-08-07 경북대학교 산학협력단 Boost circuit for standard logic processes
KR100921912B1 (en) * 2008-03-27 2009-10-16 경북대학교 산학협력단 High efficiency boost circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100740953B1 (en) * 2000-07-03 2007-07-19 가부시키가이샤 히타치세이사쿠쇼 Semiconductor integrated circuit and nonvolatile semiconductor memory
US7224616B2 (en) 2004-11-15 2007-05-29 Samsung Electronics Co., Ltd. Circuit and method for generating wordline voltage in nonvolatile semiconductor memory device
KR100674961B1 (en) * 2005-02-26 2007-01-26 삼성전자주식회사 Step-up voltage generation circuit having an additional pump circuit and a step-up voltage generation method thereof
US7576589B2 (en) 2005-02-26 2009-08-18 Samsung Electronics Co., Ltd. Boost voltage generating circuit including additional pump circuit and boost voltage generating method thereof
KR100921912B1 (en) * 2008-03-27 2009-10-16 경북대학교 산학협력단 High efficiency boost circuit
KR100911373B1 (en) * 2008-04-22 2009-08-07 경북대학교 산학협력단 Boost circuit for standard logic processes

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Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19951229

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Patent event code: PA02012R01D

Patent event date: 19951229

Comment text: Request for Examination of Application

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Patent event date: 19980930

Patent event code: PE09021S01D

E601 Decision to refuse application
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Patent event date: 19990129

Comment text: Decision to Refuse Application

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Comment text: Notification of reason for refusal

Patent event code: PE06011S01I