JP3469838B2 - Level shift circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit capable of outputting an intermediate potential, and more particularly to a level shift circuit suitable for use in a high-performance charge pump circuit. Circuit. FIG. 8 shows a conventional level shift circuit. In the circuit diagram shown in FIG.
3 is a differential MOS transistor pair, and has an input terminal IN
And the input signal and the input signal inverted by the inverter are applied to the respective gates. M13 and M14 are MOS transistors whose gates and drains are cross-connected to each other. The potential A is applied to the sources of M13 and M14, and an output voltage is obtained from the output terminal OUT. FIG. 8B is an operation waveform diagram of the level shift circuit. When the input voltage of the amplitude Vdd changes between 0 V and Vdd, the output voltage becomes a level shift voltage of the amplitude A that changes between 0 V and A (A> Vdd). [0004] As described above, according to the level shift circuit, an input signal can be converted into an arbitrary amplitude with reference to Vss (0 V). However, the conventional level shift circuit cannot output an intermediate potential between a high potential and a low potential (0 V) because Vss (0 V) is used as a reference. For this reason, in a circuit such as a charge pump circuit that frequently performs level shift, the degree of freedom in circuit design is small, and it has been difficult to sufficiently improve circuit performance. The present invention has been made in view of the above problems, and has as its object to provide a level shift circuit capable of outputting an intermediate potential, and particularly to improve the performance of a charge pump circuit. A level shift circuit according to the present invention comprises: a first transistor pair to which a complementary input signal is applied; a first transistor pair connected in series to the first transistor pair; and a gate and a drain. Are cross-connected to each other, a second transistor pair having a first potential applied to the source, a first output transistor having the first potential applied to the source, and a second transistor having the second potential applied to the source. And a second output transistor, wherein one connection node voltage of the first and second transistor pairs is applied to the gate of the first output transistor, and the other connection node voltage is applied to the gate of the second pull-up transistor. Then, an intermediate level shift voltage is output from the drains of the first and second output transistors. According to this means, since the first and second output transistors are provided, it is possible to output the first potential or the second potential according to the complementary input signal, that is, to output the intermediate potential. become. An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a diagram showing a circuit configuration and operation waveforms of an inversion level shift circuit according to an embodiment of the present invention. As shown in FIG. 1A, this inversion level shift circuit includes a MOS transistor pair M11 to which a complementary signal is input by an input inverter INV.
And M12, a cross-connected MOS transistor pair M
13 and M14. The configuration so far is the same as that of the conventional level shift circuit. The level shift circuit further includes first and second output MOS transistors M15 and M16 connected in a pull-up manner. The voltage V12 is applied to the gate of the MOS transistor M15, and the potential A is applied to the source. Also, M
A voltage V11 having a phase opposite to that of V12 is applied to the gate of the OS transistor M15, and a potential B is applied to the source of the OS transistor M15. Here, potential A> potential B. Also, M1
1, M12 is an N-channel type, and M13 to M16 are a P-channel type. FIG. 2 shows an operation waveform of this level shift circuit.
It is shown in (B). While a conventional level shift circuit outputs a high voltage and 0 V, this level shift circuit is characterized in that it outputs a potential A and an intermediate potential B (A>B> 0 V) alternately. FIG. 2 is a diagram showing a circuit configuration and operation waveforms of the non-inverting level shift circuit according to the embodiment of the present invention.
The difference from the inversion level shift circuit is that, as shown in FIG. 2A, the voltage V11 is applied to the gate of the output MOS transistor M15 pulled up to the potential A, and the MOS transistor M16 pulled up to the potential B. Is that the voltage V12 is applied to the gates of the two. Therefore, as shown in the operation waveform diagram of FIG. 2B, a non-inverting level shift operation is performed on the non-inverting level shift circuits S3 and S4 input voltage IN. By using these level shift circuits, as described later, it is possible to make the voltage between the gate and the drain of the MOS transistor for charge transfer of the charge pump circuit uniform, thereby achieving high performance. FIG. 3 is a diagram showing another embodiment of the inversion level shift circuit. The difference from the inversion level shift circuit shown in FIG. 1 is that the source of the pull-up output MOS transistor M15 has the potential C (potential different from the potentials A and B).
Is applied. This level shift circuit is shown in FIG.
As shown in the operation waveform diagram of (b), the potential C and the potential B (C
>B> 0 V). Thus, the degree of freedom in designing the level shift circuit can be further increased. Next, a level shift circuit corresponding to a negative voltage will be described. FIG. 4 is a diagram showing a negative voltage compatible inversion level shift circuit. As shown in FIG. 4A, this inversion level shift circuit includes a MOS transistor pair M23 to which a complementary signal is input by an input inverter INV.
And M24, a cross-connected MOS transistor pair M
21 and M22. Further, the first and second output MOS transistors M25 and M26 connected in a pull-down manner
It has. The voltage V22 is applied to the gate of the MOS transistor M25, and the negative potential -Vdd is applied to the source of the MOS transistor M25. A voltage V21 having a phase opposite to that of V22 is applied to the gate of the MOS transistor M25, and a potential B is applied to the source of the MOS transistor M25. Here, potential B> −V
dd. M21, M22, M25, and M26 are N-channel types, and M23 to M24 are P-channel types.
This level shift circuit is characterized in that the potential B and -Vdd are alternately output as shown in the operation waveform diagram of FIG. FIG. 5 is a diagram showing a non-inverting level shift circuit corresponding to a negative voltage. The difference from the inversion level shift circuit shown in FIG. 4 is that, as shown in FIG. 5A, the voltage V21 is applied to the gate of the output MOS transistor M25, and the voltage V22 is applied to the gate of the output MOS transistor M26. Is a point. Therefore, as shown in the operation waveform diagram of FIG. 2B, this non-inverting level shift circuit S3,
A non-inverting level shift operation is performed on the S4 input voltage IN. Next, an example in which the above-described level shift circuit is applied to a charge pump circuit will be described. FIG. 6 is a schematic circuit diagram showing a three-stage charge pump circuit according to the embodiment of the present invention. In FIG. 6, four charge transfer MOSs
The transistors M1 to M4 are connected in series. One feature is that M1 and M2 in the first stage are N-channel type, and M3 and M4 in the second stage are P-channel type. The source and the substrate are connected to have the same potential so that the gate-to-substrate voltage Vgb of M1 to M4 has the same value as the gate-to-source voltage Vgs. The input voltage V is applied to the source of M1.
The power supply voltage Vdd is supplied as in. Also, M
The boosted voltage Vout is output from the drain 4 and supplied to the current load LOAD. C1, C2, and C3 are coupling capacitors each having one end connected to a connection point (pumping node) of the charge transfer MOS transistors M1 to M4. A clock pulse CLK and a clock pulse CLKB having a phase opposite thereto are alternately applied to the other ends of the coupling capacitors C1 to C3. The clock pulses CLK and CLKB are output from a clock driver (not shown). Charge transfer MOS transistors M1 and M2
Are supplied with the outputs of the inversion level shift circuits S1 and S2. A non-inverting level shift circuit S is provided at each gate of the charge transfer MOS transistors M3 and M4.
The outputs of 3 and S4 are provided. The connection relationship between the inversion level shift circuits S1 and S2, the non-inversion level shift circuits S3 and S4, and the charge pump circuit is as follows. Inverting level shift circuit S
1 is applied with a clock pulse CLK ', and the inversion level shift circuit S1 is applied with a clock pulse CLKB'. The clock pulses CLK 'and CLKB' are generated from the clock pulses CLK and CLKB, respectively,
In order to prevent a current from flowing back to the transistors M1 to M4, a low period is long. That is, after the charge transfer MOS transistors M1 to M4 are completely turned off, the voltage of each pumping node is boosted by the change of the clock pulses CLK and CLKB. FIG. 4 shows the phase relationship between the clock pulses. Further, the clock pulse CL having such an operation is provided.
K ′ and CLKB ′ can be created by a conventional type level shift circuit. As shown in FIG. 6, as the power supply (potential A) on the high potential side of the inversion level shift circuit S1, the boosted voltage V2 of the pumping node after one stage is returned and used. Similarly, the voltage V3 of the pumping node after one stage, which has been boosted, is used as the power supply (potential A) on the high potential side of the inversion level shift circuit S2. Further, as the power supply (potential B) on the low potential side of the inversion level shift circuits S1 and S2, the voltages Vdd and V1 of the respective stages are applied, respectively. On the other hand, as the power supply (potential B) on the low potential side of the non-inverting level shift circuit S3, the voltage V1 of the pumping node one stage before is used. As the power supply (potential B), the voltage V2 of the pumping node one stage before is used. Further, as the power supply (potential A) on the high potential side of the inversion level shift circuits S1 and S2, the voltages V3 and Vout of the respective stages are used.
Are respectively applied. The features of the above-described charge pump circuit according to the present embodiment are summarized as follows. First, the two preceding charge transfer MOS transistors M1 and M2 are N
The point is that the latter two charge transfer MOS transistors M3 and M4 are of a P-channel type. Second, inverting level shift circuits S1 and S2 enabling output of an intermediate potential, and non-inverting level shift circuit S3
And S4. With these configurations, the gate-source voltage Vgs (when the transistors are on) of the charge transfer transistors M1 to M4 can be made equal to 2 Vdd as described below. Vgs (M1) = V2 (High) -Vdd Vgs (M2) = V3 (High) -V1 (High) Vgs (M3) = V1 (Low) -V3 (Low) Vgs (M4) = V2 (Low) -Vout By the way, from the boost operation of the charge pump in the steady state,
The following relationship holds: V1 (High) = 2Vdd, V1 (Low) = Vdd V2 (High) = 3Vdd, V2 (Low) = 2Vdd V3 (High) = 4Vdd, V3 (Low) = 3Vdd, Vou
t = 4 Vdd From these relational expressions, the absolute value of Vgs of all the charge transfer MOS transistors is the same value 2 Vdd as shown in Table 1.
Is derived. Therefore, the on-resistance of the charge transfer MOS transistors M1 to M4 is reduced by the high Vgs, and a charge pump circuit with high efficiency and large output current can be realized. Also, the charge transfer MOS transistors M1 to M1
Since the gate oxide film thickness of M4 may be designed to be uniform enough to withstand 2 Vdd, the on-resistance can be designed to be lower and the efficiency is higher than when the Vgs of the charge transfer MOS transistor is not uniform. [Table 1] FIG. 7 is a timing chart for explaining the operation of the charge pump circuit. The charge transfer MOS transistors M1 to M4 alternately turn on and off in response to a clock pulse. According to the present invention, a level shift circuit capable of outputting an intermediate potential can be provided, and the degree of freedom in circuit design can be expanded. Particularly, by applying the present invention to a charge pump circuit, performance can be improved. More specifically, since the source-drain voltage and the source-substrate voltage of the transfer MOS transistor can be made constant (eg, 2 Vdd), the source-drain voltage Vgs of the charge transfer MOS transistor is not uniform. The on-resistance can be designed to be lower than in the case of

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an inversion level shift circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a non-inverting level shift circuit according to an embodiment of the present invention. FIG. 3 is a circuit diagram showing an inversion level shift circuit according to another embodiment of the present invention. FIG. 4 is a circuit diagram showing a negative voltage compatible inversion level shift circuit according to an embodiment of the present invention. FIG. 5 is a circuit diagram illustrating a non-inverting level shift circuit corresponding to a negative voltage according to the embodiment of the present invention. FIG. 6 is a diagram showing a charge pump circuit to which the level shift circuit of the present invention is applied. FIG. 7 is a timing chart for explaining the operation of the charge pump circuit according to the embodiment of the present invention. FIG. 8 is a diagram showing a non-inverting level shift circuit according to a conventional example. [Description of Signs] M11, M12 First MOS transistor pair M13, M14 Second MOS transistor pair M15 First pull-up transistor M16 Second pull-up transistor

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 19/0185

Claims (1)

(57) [Claim 1] A complementary input signal is applied to a gate and a source is applied.
A first transistor pair to which a ground potential is applied, and a gate and a drain which are connected in series with the first transistor pair and whose gate and drain are cross-connected to each other, the first potential
A second transistor pair to which A is applied, a first output transistor to which a first potential A is applied to a source, and a second output transistor to which a second potential B is applied to a source. First potential A> second potential B> ground potential,
And the connection node voltage of one of the first and second transistor pairs is applied to the gate of the first transistor, and the other connection node voltage is applied to the gate of the second transistor. 1, the commonly connected drains of the second output transistor, said complementary
A level shift circuit that outputs a first potential A and a second potential B alternately in response to a signal .