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KR970024198A - Contact Forming Method of Semiconductor Device - Google Patents

Contact Forming Method of Semiconductor Device Download PDF

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Publication number
KR970024198A
KR970024198A KR1019950034566A KR19950034566A KR970024198A KR 970024198 A KR970024198 A KR 970024198A KR 1019950034566 A KR1019950034566 A KR 1019950034566A KR 19950034566 A KR19950034566 A KR 19950034566A KR 970024198 A KR970024198 A KR 970024198A
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South Korea
Prior art keywords
conductive layer
forming
layer
insulating layer
entire surface
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KR1019950034566A
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Korean (ko)
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KR0183742B1 (en
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김병철
조상연
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김광호
삼성전자 주식회사
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Priority to KR1019950034566A priority Critical patent/KR0183742B1/en
Publication of KR970024198A publication Critical patent/KR970024198A/en
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Publication of KR0183742B1 publication Critical patent/KR0183742B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

신규한 반도체 메모리장치의 제조방법이 개시되어 있다. 소오스/드레인 영역 및 게이트전극을 구비한 트랜지스터 및 상기 소오스/드레인 영역의 일부에 접속되는 제1 도전층이 형성되어 있는 반도체기판 전면에 평탄화층 및 제2 절연층을 차례로 형성한 후, 사진식각 공정으로 이방성 식각하여 제1 도전층 및 소오스/드레인 영역의 일부분을 노출시키는 비트라인 콘택과 커패시터 콘택을 동시에 형성한다. 결과물 상에 제2 도전층 및 제2 절연층을 차례로 형성한 후, 사진식각 공정으로 패터닝하여 비트라인을 형성한다. 결과물 상에 제3 도전층을 형성한 후, 사진식각 공정으로 패터닝하여 커패시터의 스토리지전극을 형성한다. 공정을 단순화시킬 뿐만 아니라, 셀 커패시턴스의 감소없이 콘택불량을 억제할 수 있다.A novel method of manufacturing a semiconductor memory device is disclosed. After forming a planarization layer and a second insulating layer on the entire surface of the semiconductor substrate having a transistor having a source / drain region and a gate electrode and a first conductive layer connected to a portion of the source / drain region, a photolithography process Anisotropic etching is performed to simultaneously form a bit line contact and a capacitor contact exposing a portion of the first conductive layer and the source / drain region. The second conductive layer and the second insulating layer are sequentially formed on the resultant, and then patterned by photolithography to form bit lines. After forming the third conductive layer on the resultant, it is patterned by a photolithography process to form a storage electrode of the capacitor. In addition to simplifying the process, contact failures can be suppressed without reducing cell capacitance.

Description

반도체장치의 콘택 형성방법Contact Forming Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2F도는 본 발명의 제1 실시예에 의한 반도체 메모리장치의 제조방법을 설명하기 위한 단면도들.2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with a first embodiment of the present invention.

Claims (9)

소오스/드레인 영역 및 게이트전극을 구비한 트랜지스터 및 상기 소오스/드레인 영역의 일부에 접속하는 제1 도전층이 형성되어 있는 반도체기판 전면에 평탄화층 및 제1 절연층을 차례로 형성하는 단계; 사진식각 공정으로 상기 평탄화층 및 제1 절연층을 이방성 식각하여 상기 제1 도전층 및 소오스/드레인 영역의 일부분을 노출시키는 비트라인 콘택과 커패시터 콘택을 동시에 형성하는 단계; 상기 결과물 전면에 제2 도전층 및 제2 절연층을 차례로 형성하는 단계; 사진식각 공정으로 상기 제2 절연층 및 제2 도전층을 패터닝하여 비트라인을 형성하는 단계; 상기 결과물 전면에 제3 도전층을 형성하는 단계; 및 사진식각 공정으로 상기 제3 도전층을 패터닝하여 커패시터의 스토리지전극을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 메모리장치의 제조방법.Sequentially forming a planarization layer and a first insulating layer on the entire surface of the semiconductor substrate having a transistor including a source / drain region and a gate electrode and a first conductive layer connected to a portion of the source / drain region; Anisotropically etching the planarization layer and the first insulating layer by a photolithography process to simultaneously form a bit line contact and a capacitor contact exposing a portion of the first conductive layer and a source / drain region; Sequentially forming a second conductive layer and a second insulating layer on the entire surface of the resultant product; Patterning the second insulating layer and the second conductive layer by a photolithography process to form a bit line; Forming a third conductive layer on the entire surface of the resultant product; And patterning the third conductive layer to form a storage electrode of the capacitor by a photolithography process. 제1항에 있어서, 상기 제3 도전층을 형성하는 단계 전에, 상기 비트라인이 형성된 결과물 전면에 제3 절연층을 형성하는 단계; 및 상기 제3 절연층을 이방성 식각함으로써 상기 비트라인의 측벽에 스페이서를 형성하는 단계를 더 구비하는 것을 특징으로 하는 반도체 메모리장치의 제조방법.The method of claim 1, further comprising: forming a third insulating layer on the entire surface of the product on which the bit line is formed before the forming of the third conductive layer; And forming a spacer on a sidewall of the bit line by anisotropically etching the third insulating layer. 제2항에 있어서, 상기 스페이서 및 제2 절연층에 의해 상기 제3 도전층과 제2 도전층이 서로 전기적으로 분리되는 것을 특징으로 하는 반도체메모리장치의 제조방법.The method of claim 2, wherein the third conductive layer and the second conductive layer are electrically separated from each other by the spacer and the second insulating layer. 제2항에 있어서, 상기 제3 절연층은 실리콘질화물을 1000∼3000Å 두께로 침적하여 형성하는 것을 특징으로 하는 반도체 메모리장치의 제조방법.3. The method of claim 2, wherein the third insulating layer is formed by depositing silicon nitride in a thickness of 1000 to 3000 GPa. 제1항에 있어서, 상기 제1 및 제2 절연층은 실리콘질화물을 1000∼3000Å 두께로 침적하여 형성하는 것을 특징으로 하는 반도체 메모리장치의 제조방법.The method of claim 1, wherein the first and second insulating layers are formed by depositing silicon nitride in a thickness of 1000 to 3000 GPa. 제1항에 있어서, 상기 제2 도전층은 폴리사이드 또는 텅스텐 중의 어느 하나를 1000∼3000Å 두께로 침적하여 형성하는 것을 특징으로 하는 반도체 메모리장치의 제조방법.The method of claim 1, wherein the second conductive layer is formed by depositing any one of polysides or tungsten to a thickness of 1000 to 3000 GPa. 소오스/드레인 영역 및 게이트전극을 구비한 트랜지스터 및 상기 소오스/드레인 영역의 일부에 접속되는 제1 도전층이 형성되어 있는 반도체기판 전면에 제1 평탄화층을 형성하는 단계; 사진식각 공정으로 상기 제1 평탄화층을 이방성 식각하여 상기 제1 도전층 및 소오스/드레인 영역의 일부분을 노출시키는 비트라인 콘택과 제1 커패시터 콘택을 동시에 형성하는 단계; 상기 결과물 전면에 제2 도전층 및 제1 절연층을 차례로 형성하는 단계; 사진식각 공정으로 상기 제1 절연층 및 제2 도전층을 패터닝하여 비트라인을 형성하는 단계; 상기 결과물 전면에 제2 평탄화층 및 제3 절연층을 차례로 형성하는 단계; 사진식각 공정으로 상기 제3 절연층 및 제2 평탄화층을 이방성 식각하여 제2 커패시터 콘택을 형성하는 단계; 상기 결과물 전면에 제3 도전층을 형성하는 단계; 및 사진식각 공정으로 상기 제3 도전층을 패터닝하여 커패시터의 스토리지전극을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 메모리장치의 제조방법.Forming a first planarization layer on an entire surface of a semiconductor substrate on which a transistor having a source / drain region and a gate electrode and a first conductive layer connected to a portion of the source / drain region are formed; Anisotropically etching the first planarization layer by a photolithography process to simultaneously form a bit line contact and a first capacitor contact exposing a portion of the first conductive layer and a source / drain region; Sequentially forming a second conductive layer and a first insulating layer on the entire surface of the resultant product; Forming a bit line by patterning the first insulating layer and the second conductive layer by a photolithography process; Sequentially forming a second planarization layer and a third insulating layer on the entire surface of the resultant product; Anisotropically etching the third insulating layer and the second planarization layer by a photolithography process to form a second capacitor contact; Forming a third conductive layer on the entire surface of the resultant product; And patterning the third conductive layer to form a storage electrode of the capacitor by a photolithography process. 제7항에 있어서, 상기 제2 평탄화층을 형성하는 단계 전에, 상기 비트라인이 형성된 결과물 전면에 제2 절연층을 형성하는 단계; 및 상기 제2 절연층을 이방성 식각함으로써 상기 비트라인의 측벽에 스페이서를 형성하는 단계를 더 구비하는 것을 특징으로 하는 반도체 메모리장치의 제조방법.The method of claim 7, further comprising: forming a second insulating layer on an entire surface of the resultant product on which the bit line is formed before forming the second planarization layer; And forming a spacer on a sidewall of the bit line by anisotropically etching the second insulating layer. 제7항에 있어서, 상기 제2 커패시터 콘택의 형성시, 상기 제1 커패시터 콘택 내에 채워진 상기 제2 도전층을 노출시키는 것을 특징으로 하는 반도체 메모리장치의 제조방법.The method of claim 7, wherein the forming of the second capacitor contact exposes the second conductive layer filled in the first capacitor contact. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950034566A 1995-10-09 1995-10-09 Contact Forming Method of Semiconductor Device KR0183742B1 (en)

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KR1019950034566A KR0183742B1 (en) 1995-10-09 1995-10-09 Contact Forming Method of Semiconductor Device

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KR970024198A true KR970024198A (en) 1997-05-30
KR0183742B1 KR0183742B1 (en) 1999-03-20

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100486610B1 (en) * 1997-12-30 2005-09-02 주식회사 하이닉스반도체 Method for manufacturing capacitor of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100486610B1 (en) * 1997-12-30 2005-09-02 주식회사 하이닉스반도체 Method for manufacturing capacitor of semiconductor device

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KR0183742B1 (en) 1999-03-20

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