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KR970019082A - Exclusive OR operation unit - Google Patents

Exclusive OR operation unit Download PDF

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Publication number
KR970019082A
KR970019082A KR1019950032996A KR19950032996A KR970019082A KR 970019082 A KR970019082 A KR 970019082A KR 1019950032996 A KR1019950032996 A KR 1019950032996A KR 19950032996 A KR19950032996 A KR 19950032996A KR 970019082 A KR970019082 A KR 970019082A
Authority
KR
South Korea
Prior art keywords
exclusive
complementary transfer
input terminal
present
operation unit
Prior art date
Application number
KR1019950032996A
Other languages
Korean (ko)
Inventor
강신모
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950032996A priority Critical patent/KR970019082A/en
Publication of KR970019082A publication Critical patent/KR970019082A/en

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Abstract

본 발명은 배타적 논리합 연산장치에 관하여 게시한다. 본 발명에 의한 논리합 연산장치는 두 개의 상보적 전송 트랜지스터의 게이트에 하나의 입력단자를 연결하고 상기 트랜지스터의 소오스에는 다른 하나의 입력단자를 연결하며 상기 트랜지스터의 드레인에는 출력단자를 연결하여 구성한다. 본 발명에 의하여 그 크기를 감소시킬 수가 있다.The present invention relates to an exclusive OR operation apparatus. The logic sum operation apparatus according to the present invention is configured by connecting one input terminal to the gates of two complementary transfer transistors, the other input terminal to the source of the transistor, and the output terminal to the drain of the transistor. It is possible to reduce the size by the present invention.

Description

배타적 논리합 연산장치Exclusive OR operation unit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 배타적 논리합 연산장치의 논리회로도.1 is a logic circuit diagram of an exclusive OR operation apparatus of the present invention.

Claims (1)

두 개의 상보적 전송 트랜지스터에 두 개의 입력단자와 한 개의 출력단자가 연결된 배타적 논리합 논리회로에 있어서, 상기 상보적 전송 트랜지스터의 게이트에 연결된 하나의 입력단자와; 상기 상보적 전송 트랜지스터의 소오스에 연결된 다른 입력단자; 및 상기 상보적 전송 트랜지스터의 드레인에 연결된 출력단자로 구성하는 배타적 논리합 연산장치.An exclusive OR logic circuit having two input terminals and one output terminal coupled to two complementary transfer transistors, comprising: one input terminal connected to a gate of the complementary transfer transistor; Another input terminal coupled to a source of the complementary transfer transistor; And an output terminal coupled to the drain of the complementary transfer transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950032996A 1995-09-29 1995-09-29 Exclusive OR operation unit KR970019082A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950032996A KR970019082A (en) 1995-09-29 1995-09-29 Exclusive OR operation unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950032996A KR970019082A (en) 1995-09-29 1995-09-29 Exclusive OR operation unit

Publications (1)

Publication Number Publication Date
KR970019082A true KR970019082A (en) 1997-04-30

Family

ID=66616112

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950032996A KR970019082A (en) 1995-09-29 1995-09-29 Exclusive OR operation unit

Country Status (1)

Country Link
KR (1) KR970019082A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100361505B1 (en) * 1999-04-12 2002-11-18 주식회사 서진인스텍 Level transmitter with improved calibration function and calibration method of the level transmitter
KR100481846B1 (en) * 1998-06-29 2005-06-08 삼성전자주식회사 Exclusive or/nor gate circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100481846B1 (en) * 1998-06-29 2005-06-08 삼성전자주식회사 Exclusive or/nor gate circuit
KR100361505B1 (en) * 1999-04-12 2002-11-18 주식회사 서진인스텍 Level transmitter with improved calibration function and calibration method of the level transmitter

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19950929

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid