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KR910017424A - Memory cell circuit of semiconductor integrated circuit device - Google Patents

Memory cell circuit of semiconductor integrated circuit device Download PDF

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Publication number
KR910017424A
KR910017424A KR1019910004085A KR910004085A KR910017424A KR 910017424 A KR910017424 A KR 910017424A KR 1019910004085 A KR1019910004085 A KR 1019910004085A KR 910004085 A KR910004085 A KR 910004085A KR 910017424 A KR910017424 A KR 910017424A
Authority
KR
South Korea
Prior art keywords
channel mos
mos transistor
gate
memory cell
semiconductor integrated
Prior art date
Application number
KR1019910004085A
Other languages
Korean (ko)
Other versions
KR950000498B1 (en
Inventor
히데시 마에노
Original Assignee
시기 모리야
미쓰비시뎅끼가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 시기 모리야, 미쓰비시뎅끼가부시끼가이샤 filed Critical 시기 모리야
Publication of KR910017424A publication Critical patent/KR910017424A/en
Application granted granted Critical
Publication of KR950000498B1 publication Critical patent/KR950000498B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

반도체 집적회로 장치의 메모리셀 회로Memory cell circuit of semiconductor integrated circuit device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 한 실시예를 표시하는 메모리셀의 회로도, 제2도는 제1도의 회로의 트랜지스터 레벨의 회로도.1 is a circuit diagram of a memory cell showing one embodiment of the present invention, and FIG. 2 is a transistor level circuit diagram of the circuit of FIG.

Claims (1)

제1, 제2의 인버터호로와, 제1, 제2의 N채널 MOS트랜지스터와, 제1, 제2의 P채널 MOS트랜지스터를 구비하고, 제1, 제2의 인버터회로는 서로 출력을 다른쪽의 입력에 접속하여 데이터의 유지후프를 구성하여 이루고, 제1의 N채널 MOS트랜지스터의 드레인과 제1의 P채널 MOS트랜지스터의 드레인은 제1, 제2의 인버터 회로의 한쪽의 입출력 접속점에 접속하고, 제2의 N채널 MOS트랜지스터의 드레인과 제2의 P채널 MOS트랜지스터의 드레인은 제1, 제2의 인버터회로의 다른쪽의 입출력 접속점에 접속하고, 제1의 N채널 MOS트랜지스터의 게이트는 제2의 N채널 MOS트랜지스터의 게이트에 접속하는 것과 아울러, 제1의 P채널 MOS트랜지스터의 게이트는제2의 P채널 MOS트랜지스터의 게이트에 접속하여 이루는 것을 특징으로 하는 반도체 집적회로 장치의 메모리셀 회로.The first and second inverter arcs, the first and second N-channel MOS transistors, and the first and second P-channel MOS transistors are provided, and the first and second inverter circuits have different outputs. A data retention hoop is formed by connecting to the input of the first N-channel MOS transistor and the drain of the first P-channel MOS transistor is connected to one input / output connection point of the first and second inverter circuits. And the drain of the second N-channel MOS transistor and the drain of the second P-channel MOS transistor are connected to the other input / output connection points of the first and second inverter circuits, and the gate of the first N-channel MOS transistor is provided. And the gate of the first P-channel MOS transistor is connected to the gate of the second N-channel MOS transistor, and the gate of the second P-channel MOS transistor is connected to the gate of the second P-channel MOS transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019910004085A 1990-03-28 1991-03-14 Memory cell circuit of semiconductor integrated circuit device KR950000498B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2-79625 1990-03-28
JP2079625A JPH03280294A (en) 1990-03-28 1990-03-28 Memory cell circuit of semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
KR910017424A true KR910017424A (en) 1991-11-05
KR950000498B1 KR950000498B1 (en) 1995-01-24

Family

ID=13695260

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910004085A KR950000498B1 (en) 1990-03-28 1991-03-14 Memory cell circuit of semiconductor integrated circuit device

Country Status (3)

Country Link
JP (1) JPH03280294A (en)
KR (1) KR950000498B1 (en)
DE (1) DE4110140A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2720104B2 (en) * 1990-09-04 1998-02-25 三菱電機株式会社 Memory cell circuit of semiconductor integrated circuit device
EP0578915A3 (en) * 1992-07-16 1994-05-18 Hewlett Packard Co Two-port ram cell
JP3214132B2 (en) * 1993-03-01 2001-10-02 三菱電機株式会社 Memory cell array semiconductor integrated circuit device

Also Published As

Publication number Publication date
KR950000498B1 (en) 1995-01-24
DE4110140A1 (en) 1991-10-02
JPH03280294A (en) 1991-12-11

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