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KR970019031A - Phase Shift Circuit with Selectable Phase Delay - Google Patents

Phase Shift Circuit with Selectable Phase Delay Download PDF

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Publication number
KR970019031A
KR970019031A KR1019950031697A KR19950031697A KR970019031A KR 970019031 A KR970019031 A KR 970019031A KR 1019950031697 A KR1019950031697 A KR 1019950031697A KR 19950031697 A KR19950031697 A KR 19950031697A KR 970019031 A KR970019031 A KR 970019031A
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South Korea
Prior art keywords
output
phase delay
phase
delay unit
input
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KR1019950031697A
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Korean (ko)
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KR0153046B1 (en
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이동철
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

본 발명은 위상 변환 회로에 관한 것으로서 특히, 입력 값에 따라 위상 지연을 선택할 수 있는 위상 변환 회로에 관한 것이다.The present invention relates to a phase shift circuit, and more particularly, to a phase shift circuit capable of selecting a phase delay according to an input value.

본 발명은 데이터 입력 단자에서 인가된 데이터 신호를 복수 개의 위상이 지연된 데이터 신호로 복수 개의 출력 단자에 출력하는 위상 지연부; 및 상기 위상 지연부의 복수 개의 지연된 데이터 신호를 입력으로 하여 선택 단자에서 인가된 선택 신호에 따라 상기 복수 개의 출력중 어느 한 신호를 선택하여 출력하는 선택부로 구성된 것을 특징으로 한다.According to an embodiment of the present invention, a phase delay unit outputs a data signal applied from a data input terminal to a plurality of output terminals as a plurality of phase delayed data signals; And a selector configured to input one of the plurality of delayed data signals of the phase delay unit to select one of the plurality of outputs according to a selection signal applied from a selection terminal and to output the selected signal.

따라서 본 발명은 위상 지연부와 선택부를 결합하여 선택 단자의 선택 신호에 따라 출력 값을 원하는 만큼 지연시켜 출력할 수 있으므로 다른 신호와 동기를 취할 때 용이하다.Therefore, the present invention can be combined with the phase delay unit and the selector to delay and output the output value as desired according to the selection signal of the selection terminal, thereby facilitating synchronization with other signals.

Description

위상 지연을 선택할 수 있는 위상 변환 회로Phase Shift Circuit with Selectable Phase Delay

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 실시예를 보여주는 회로 구성도,2 is a circuit diagram showing an embodiment according to the present invention,

제3도 내지 제6도는 선택 단자 PHASE<2:1>의 선택 신호에 따라 출력 형태를 보여주는 타이밍도.3 through 6 are timing diagrams showing output shapes according to selection signals of the selection terminals PHASE <2: 1>.

Claims (5)

위상 변환 회로에 있어서, 데이터 입력 단자에서 인가된 데이터 신호를 복수 개의 위상이 지연된 데이터 신호로 복수 개의 출력 단자에 출력하는 위상 지연부; 및 상기 위상 지연부의 복수 개의 지연된 데이터 신호를 입력으로 하여 선택 단자에서 인가된 선택 신호에 따라 상기 복수 개의 출력중 어느 한 신호를 선택하여 출력하는 선택부로 구성된 것을 특징으로 하는 위상 지연을 선택할 수 있는 위상 변환 회로.A phase shift circuit comprising: a phase delay unit for outputting a data signal applied from a data input terminal to a plurality of output terminals as a plurality of phase delayed data signals; And a selector configured to input a plurality of delayed data signals of the phase delay unit to select one of the plurality of outputs according to a selection signal applied from a selection terminal and to output the selected signal. Conversion circuit. 제1항에 있어서, 상기 위상 지연부는 복수 개의 플립-플롭으로 구성되며, 각 플립-플롭은 클럭 단자에 외부 입력 신호가 공통으로 인가되고, 상기 각 플립-플롭의 데이터 단자에 전 단의 플립-플롭의 출력이 인가되고, 또한 상기 각 플립-플롭은 다음 단에 인가되는 데이터 신호와 동일한 신호를 출력하는 출력 단자를 갖는 것을 특징으로 하는 위상 지연을 선택할 수 있는 위상 변환 회로.2. The apparatus of claim 1, wherein the phase delay unit includes a plurality of flip-flops, each flip-flop having an external input signal applied to a clock terminal in common, and a flip-flop at the front end of each flip-flop. And the output of the flop is applied, and each of the flip-flops has an output terminal for outputting the same signal as the data signal applied to the next stage. 제2항에 있어서, 상기 위상 지연부는 입력된 데이터 신호가 위상 지연 없이 출력되는 출력 단자를 더 구비하는 것을 특징으로 하는 위상 지연을 선택할 수 있는 위상 변환 회로.The phase shift circuit as claimed in claim 2, wherein the phase delay unit further includes an output terminal through which an input data signal is output without phase delay. 제1항에 있어서, 상기 선택부는 상기 선택 단자에서 입력되는 선택 신호에 따라 선택되는 복수 개의 출력을 갖는 디코더; 및 상기 위상 지연부의 복수 개의 출력과 상기 디코더의 복수 개의 출력을 입력으로 하여 하나의 출력을 갖는 출력부로 구성된 것을 특징으로 하는 위상 지연을 선택할 수 있는 위상 변환 회로.The apparatus of claim 1, wherein the selector comprises: a decoder having a plurality of outputs selected according to a selection signal input from the selection terminal; And an output unit having a single output by inputting a plurality of outputs of the phase delay unit and a plurality of outputs of the decoder as inputs. 제4항에 있어서, 상기 출력부는 상기 위상 지연부에서 출력되는 복수 개의 출력 신호와 상기 디코더에서 출력되는 복수 개의 출력 신호를 대응하는 각각 낸드 게이트의 입력으로 하여 상기 각각 낸드 게이트를 통해 출력되고, 상기 각 낸드 게이트의 출력을 조합하는 출력용 낸드 게이트를 통해 선택된 값을 출력하는 것을 특징으로 하는 위상 지연을 선택할 수 있는 위상 변환 회로.The method of claim 4, wherein the output unit is a plurality of output signals output from the phase delay unit and a plurality of output signals output from the decoder are output through the respective NAND gates respectively corresponding to the input of the NAND gate, A phase shift circuit capable of selecting a phase delay, characterized in that for outputting a selected value through an output NAND gate combining the outputs of each NAND gate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950031697A 1995-09-25 1995-09-25 Phase converting circuit enable to select phase delay Expired - Fee Related KR0153046B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950031697A KR0153046B1 (en) 1995-09-25 1995-09-25 Phase converting circuit enable to select phase delay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950031697A KR0153046B1 (en) 1995-09-25 1995-09-25 Phase converting circuit enable to select phase delay

Publications (2)

Publication Number Publication Date
KR970019031A true KR970019031A (en) 1997-04-30
KR0153046B1 KR0153046B1 (en) 1998-12-15

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KR0153046B1 (en) 1998-12-15

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