KR920015178A - Variable generation circuit of bale signal - Google Patents

Abstract

No content

Description

Variable generation circuit of bale signal

Since this is an open matter, no full text was included.

2 is a variable generation circuit diagram of a BALE signal according to the present invention. 3 is a detailed circuit diagram of the decoder of FIG.

Claims (6)

Decoder (1), (4) for decoding the lower two bits (A ₁ , A _a ) signal and the upper two bits (A ₃ , A ₂ ) of variable mode signal (3: 0), respectively, and ALE signal (ALE) ALE signal delay to delay the "0.1, 2, 3" clock of main clock (NCLK) and generate delayed ALE signal inactive for the same timing according to the width control signal (Q _N1 -Q _N4 ). Delay signal selection output that the decoder 1 _{selects and} outputs one of the section 2 and the outputs Q _N1 -Q _N4 of the ALE signal delay section 2 according to the decoding outputs Y _0N -Y _3N . The output of the delay signal selection output section 3 and the output section 3 are sequentially shifted so that the " 0 ", 1, 2, 3 " clocks of the main clock NCLK are delayed, and the timing is equalized according to the end signal END. One of the width control signal generator 5 for generating the width control signal inactive (Q _N5 -Q _N8 ) and the output (Q _N5 -Q _N8 ) of the width control signal generator 5 is selected from the decoder ( The ALE signal is selected according to the decoding output (Y _0N -Y _3N ) of 4). The width control signal selection output section 6 outputting the width control signal to the call delay section 2, the width control signal of the width control signal selection output section 6, and the delayed ALE of the delay signal selection output section 3; And a BALE signal output section (7) for combining the signals to output a BALE signal (BALE) having a delay time and a width controlled in accordance with the mode signal (3: 0). The preset signal of the flip-flop (F / F ₁ ) of the ALE signal delay unit 2, the ALE signal delay unit (2). By applying the non-inverting output (Q) of the front end to the input (D) of the next stage, and feeds back the non-inverting output (Q) of the flip-flop (F / F ₁ ) to its second input (T ₁ ). The input of the flip-flop F / F ₁ receives the output of the AND gate AND ₁ receiving the reset signal NRST on one side and the width control signal of the tactile control signal selection output unit 6 on the other side. The clock synchronization clear signal is applied to the selection signal T _g and the first input D thereof. Is common to the flip-flops F / F ₁ -F / F ₄ , and the main clock NCLK is connected to the flip-flops F / F ₁ -F / F ₄ through an inverter I ₂ . A variable BALE signal, characterized in that configured to output the inverted outputs Q _N1 -Q _{4 of} the flip-flops F / F ₁ -F / F _{4 as} delayed ALE signals by being applied as a signal CK. Generating circuit. The delay signal selector 3 outputs the inverted outputs Q _N1 -Q _N4 of the ALE signal delay units 2 and the flip-flops F / F ₁ -F / F ₄ . ALE signal delayed by combining the decoding outputs (Y _0N -Y _3N ) and NOR gates (NR ₁ -NR ₄ ) and then combining the outputs of the NOR gates (NR ₁ -NR ₄ ) at the NOA gate (NR ₅ ). The variable generation circuit of the BALE signal, characterized in that configured to selectively output. The width control signal generator 5 receives the output of the delay signal selection output unit 3 as an input D signal of the flip-flop F / F ₅ through the inverter I ₃ . In this case, the non-inverting output (Q) at the front end is applied to the next input (D) to sequentially shift the flip-flop (F / F ₅ -F / F ₈ ), and the main clock signal (NCLK) through the inverter (I ₄ ). ) Is applied to the common clock CK and the inverted output (F / F ₅ -F / F ₈ ) of the flip-flop F / F ₅ -F / F ₈ , which receives the end END through the inverter I ₅ , as the clock synchronous clear signal CSN. QN ₅ -QN ₈ ) is a variable generation circuit of the BALE signal characterized in that it is configured to output each as a width control signal. 2. The width control signal selection output section 6 is the inversion output QN ₅ -QN ₈ of the width control signal generation section 5 and the flip-flops F / F ₅ -F / F ₈ and the decoder ( ₆ ). the decoded output (Y _0N -Y _3N) of 4), each in combination with the NOR gate (NR ₆ -NR ₉₎ the NOR gate (NOR gate NR ₆ -NR (NR _10), an output of ⁹⁾ and then combined with A variable generation circuit for a BALE signal, characterized in that it is configured to selectively output a width control signal. 2. The BALE signal output section 7 inverts the width control signal of the width control signal selection output section 6 through the inverter I ₆ and then outputs the delay selection output section 3 and the noar gate. A variable generation circuit for a BALE signal, characterized in that configured to output as a BALE signal (BALE) by combining through (NR ₁₁ ). ※ Note: The disclosure is based on the initial application.