KR970008943A - Short burst direct acquisition Direct sequential frequency spreading receiver - Google Patents

Abstract

The present invention relates to a detailed description and circuit of a direct sequence (DS) frequency spreading baseband receiver. The application of the baseband receiver is a short data burst application where it is required to quickly acquire it before continuing with reliable data demodulation. The present invention is also suitable for a DS receiver using various types of antennas by sequentially processing each separate antenna input signal. The embodiments of the present invention also have the advantage of being able to minimize the size and cost of the device, but have high performance.

Description

Short burst direct acquisition Direct sequential frequency spreading receiver

Since this is a trivial issue, I did not include the contents of the text.

FIG. 2 is a functional block diagram of a communication transceiver; FIG. 3 is a block diagram of a Barebands processor that can be used in the transceiver of FIG. 2; FIG. Functional block diagram.

Claims (8)

CLAIMS What is claimed is: 1. A communication method, comprising: transmitting a broadcast signal modulated by a pseudo random noise (PN) modulation scheme and a data signal representing data to be transmitted modulated in a phase shift scheme; A system for receiving radio frequency (RF) communications, comprising: a plurality of antennas; an antenna selection switch for selectively connecting one of the plurality of antennas to the remainder of the system; An RF / IF converter for down-converting an RF signal received on the one of the plurality of antennas to generate an intermediate frequency signal from the RF signal; A quadrature IF demodulator that demodulates into the band and provides quadrature I and Q baseband signals from the intermediate frequency signal and a quadrature IF demodulator that receives the I and Q signals and provides digital data signals related to data communicated from the received signals And a digital baseband processor; The baseband processor includes an analog-to-digital converter for converting the I and Q signals into digital I and Q signals, two co-relators for de-spreading the digital signal on one of the I and Q channels respectively, And a polarizer for converting the Q channel to a polar coordinate, a phase locked loop PSK demodulator for demodulating data symbols from the polar coordinates, a data descrambler for descrambling the demodulated data, and a demodulator for demodulating and demodulating the demodulated, And a serial interface provided to an external device. 2. The circuit system of claim 1, wherein the baseband processor is mounted in a single device, and preferably is mounted in a single monolithic device. 3. A device according to claim 1 or 2, characterized in that it comprises an arrangement for compensating for drift in the A / D converter, the device being provided for disabling the A / D converter during the transmission of a communication signal system. 4. The circuit system of claim 3, comprising an apparatus for selectively changing the time constant of the A / D converter. 5. A circuit system as claimed in any one of claims 1 to 4, characterized in that the correlator is limited at a non-zero level for small signals and preferably performs two correlation analyzes per symbol. 6. A method according to any one of claims 1 to 5, characterized in that the despreading is performed by means of a pseudorandom noise (PN) code having selectable lengths and subdivisions, in which the received signal comprises at least two signals And wherein the means is demodulated using a quality indicator, each means having an optional threshold of detection and error capture declaration. 7. The circuit system of claim 6, wherein the quality indicator comprises one or more bit tuning amplitude and phase deviation measurements. 8. A method according to any one of claims 1 to 7, wherein the received signal is demodulated interferometrically and subsequently demodulated differentially, and wherein the clock providing a sampling period for demodulating the received symbol is reversed To-analog converter circuit. ※ Note: It is disclosed by the contents of the first application.