KR970003563A - Wiring layer planarization method of semiconductor device with uneven wiring spacing - Google Patents
Wiring layer planarization method of semiconductor device with uneven wiring spacing Download PDFInfo
- Publication number
- KR970003563A KR970003563A KR1019950019132A KR19950019132A KR970003563A KR 970003563 A KR970003563 A KR 970003563A KR 1019950019132 A KR1019950019132 A KR 1019950019132A KR 19950019132 A KR19950019132 A KR 19950019132A KR 970003563 A KR970003563 A KR 970003563A
- Authority
- KR
- South Korea
- Prior art keywords
- wiring
- semiconductor device
- wiring layer
- spacing
- uneven
- Prior art date
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 소자의 제조방법Manufacturing method of semiconductor device
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
배선 간격이 일정하지 않은 배선층의 평탄화 공정의 수행시 발생되는 배선 간격이 좁은 부분과 배선 간격이 넓은 부분의 평탄화가 차이가 생긴다는 문제점을 해결하고자 함.The purpose of the present invention is to solve a problem in that planarization between a portion having a narrow wiring gap and a portion having a large wiring gap occurs when the wiring layer is flattened.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
배선에 이용되지 않은 더미(Dummy)배선을 넓은 간격을 유지하는 배선 영역에 배치하여 배선 간격을 일정하게 유지시킴으로써 양호하게 평탄화를 이룰 수 있도록 함.Dummy wiring that is not used for wiring is placed in the wiring area keeping a wide distance to keep the wiring gap constant so that the flatness can be well achieved.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 소자의 제조에 이용됨.Used in the manufacture of semiconductor devices.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3A도 및 제3B도는 본 발명의 배선 간격이 일정하지 않은 반도체 소자의 배선층 평탄화 방법을 도시하는 도면.3A and 3B show a method of planarizing a wiring layer of a semiconductor device in which wiring intervals of the present invention are not constant.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950019132A KR970003563A (en) | 1995-06-30 | 1995-06-30 | Wiring layer planarization method of semiconductor device with uneven wiring spacing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950019132A KR970003563A (en) | 1995-06-30 | 1995-06-30 | Wiring layer planarization method of semiconductor device with uneven wiring spacing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR970003563A true KR970003563A (en) | 1997-01-28 |
Family
ID=66526532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950019132A KR970003563A (en) | 1995-06-30 | 1995-06-30 | Wiring layer planarization method of semiconductor device with uneven wiring spacing |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970003563A (en) |
-
1995
- 1995-06-30 KR KR1019950019132A patent/KR970003563A/en not_active Application Discontinuation
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19950630 |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |