KR970000392B1 - Digital transmission circuit and the method of deciding dividing rate - Google Patents

Abstract

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Description

Reference Clock Division Correction Circuit for Digital Transmission

1 is a schematic block diagram of a reference clock divider circuit for future digital transmission.

2 is a block diagram of a digital clock reference clock frequency division decision circuit according to an embodiment of the present invention.

3 is a view showing a specific embodiment of the frequency division control circuit 10 of FIG.

4 is a diagram illustrating the output waveforms of the division control circuit 10 for 1.544 MHz, and FIG. 4 b illustrates the output waveforms of the division control circuit 10 for 2.048 MHz.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a digital element circuit, in particular to input and divide a reference clock supplied from a TI network or an EI network, which is an exchange network, so as to generate a desired clock for a sub-station, for example. It's about the circuit that determines the division.

The part of the communication network that connects the switching stations is called the inter-station relay network or the main network, and the part that connects the switching station and the subscriber is called the subscriber network. The transmission line constituting the inter-network is a trunk line, and the transmission line in the subscriber network is a subscriber-loop or a customer-loop. On the other hand, the reference clock output from the exchange network is generated as a predetermined clock by the inter-station line, which is divided into the following two types. One is the TI network known as the North American type, which has one channel of 24 channels and a clock speed of 1.544 MHz. The other is an EI network known as the European method (also known as CEPT network, but will be referred to herein as an EI network), which has 32 channels in one frame and a clock speed of 2.048 MHz. These reference clocks are generated by a phase-locked loop (PLL) external reference clock, which is a phase shift loop, from a digital transmission circuit as a digital transmission line. The clock generated is 4KHz, as is well known. On the other hand, it is well known in the art that the above digital transmission circuits must be applicable regardless of whether the switch network is a TI network or an EI network.

In this regard, FIG. 1 shows a schematic block diagram of a reference clock divider circuit for digital transmission commonly used in the art. Referring to the configuration shown in FIG. 1, the reference clocks REF0, REF1, and REF2-internal networks inputted at 1.544 MHz or 2.048 MHz define three reference clocks that can be received by the network synchronizer. A selection circuit 2 for inputting-, a division circuit 4 for generating a reference clock of 4KHZ in response to the output signal of the selection circuit 2, and a division circuit 4 in response to the reference clock being input at 1.544 MHz or 2.048 MHz. It consists of a switch 6 that selects the dispense to be determined. Here, the selection circuit 2 selects a clock having a good state among three reference clocks, REF0, REF1, and REF2, and outputs the selected clock to the division circuit 4. The frequency division circuit 4 operates at 386 frequency divisions or 512 frequency divisions, and is usually composed of a counter consisting of two stages. The frequency division operation of the counter is determined by the switch 6. On the other hand, switch 6 determines whether the digital transmission circuit of FIG. 1 is used in the TI network or the EI network, and on / off of the digital transmission circuit. Is switched to the off state (or open state) so that the divider circuit 4 is divided into 386, and the switched-on state (or short state) so that the divider circuit 4 divides into 512 when the digital transmission circuit is used in the EI network. Is determined. Accordingly, in the digital transmission circuit of FIG. 1, the clock periods of the three reference clocks REF0, REF1, and REF2 must be identical to each other, and there is a restriction that information about these reference clocks must be known in advance. In addition, the frequency division decision method in such a digital transmission circuit is one of the three reference clocks, REF0, REF1, and REF2, when mixed and input at 1.544 MHz or 2.048 MHz. Since only 386 or 512 divisions are chosen, there has been a drawback that two reference clocks, 1.544 MHz and 2.048 MHz, cannot be accommodated simultaneously.

Accordingly, an object of the present invention is to provide a circuit for determining the division of the reference clock so that it can operate automatically and adaptively regardless of the type of the switching network (TI, EI).

Another object of the present invention is to provide a circuit for determining the division of the reference clock so that even if reference clocks having different frequencies (1.544MHz and 2.048MHz) are mixed and input at the same time, the reference clocks are automatically determined and accommodated simultaneously.

Still another object of the present invention is to provide a reference clock division determination circuit for digital transmission which eliminates the inconvenience of having to know information on an input frequency in advance.

In order to achieve the objects of the present invention, the present invention is directed to a digital transmission circuit that can be adapted to both the switch network and the TI network or the EI network.

The digital transmission circuit according to the present invention comprises a selection circuit which inputs a plurality of reference clocks and selects one of the highest clocks having a good state among the inputs, and divides the reference clock selected by the selection circuit according to its frequency into a phase synchronization. A divider circuit for generating a loop external reference clock, a first stage multivibrator for inputting the plurality of reference clocks, a second stage multivibrator for inputting an output of the first stage multivibrator, and a reference clock selected from the selection circuit Therefore, it is characterized in that it comprises a frequency division control circuit consisting of a multiplexer for selecting one of the output of the second stage multi-vibrator to pass to the frequency division circuit.

BEST MODE Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a reference clock division determination circuit for digital transmission according to an embodiment of the present invention. According to FIG. 2, the digital clock reference clock division decision circuit of this embodiment includes a selection circuit 8 that inputs three reference clocks REF0, REF1, and REF2 and selects one of the highest clocks having a good state among the inputs, and the selection circuit. A division circuit 12 for generating a phase locked loop external reference clock by dividing the reference clock selected in step 8 according to the frequency thereof, and a first stage multivibrator 14-1 and 16- that inputs the three reference clocks REF0, REF1, and REF2. 1, 18-1, the second stage multivibrator 14-2, 16-2, 18-2 for inputting the outputs of the first stage multivibrator 14-1, 16-1, 18-1, and the selection circuit 8. The frequency divider control circuit 10 includes a multiplexer 20 that selects one of the outputs of the second stage multivibrators 14-2, 16-2, and 18-2 according to the selected reference clock and transfers the output to the frequency divider 12. Here, the configuration of the selection circuit 8 and the frequency divider 12 can be implemented in the same configuration as that in FIG.

In this configuration, it is found that the digital clock reference clock frequency division determining circuit according to the present invention is located in the frequency division control circuit 10 that controls the frequency division operation of the frequency division circuit 12. The frequency divider control circuit 10 monitors the three reference clocks REF0, REF1, and REF2 that are input, respectively, and sets a counter value in the frequency divider 12 that matches the selected reference clock. Regardless, it automatically changes the division value to generate 4KHz.

3 is a diagram showing an embodiment of the frequency division control circuit 10 of FIG. A detailed configuration and operation of the frequency divider control circuit 10 will be described below.

The frequency divider control circuit 10 is a retriggerable monostable multivibrator capable of inputting a reference clock REF0 and output pulse width of 560 ns (nano second), hereinafter referred to as a multivibrator. 14-1, the multivibrator 14-2 which inputs the output signal of the multivibrator 14-1 and the output pulse width becomes 800ns, and the multivibrator 16-1 which inputs the reference clock REF1 and the output pulse width becomes 560ns, Multivibrator 16-1, which inputs the output signal of the multivibrator 16-1, and whose output pulse width is 800 ns., Multivibrator 18-1, which inputs the reference clock REF2 and the output pulse width is 560 ns., And Multivibrator 18-1. Inputs the output signal of the multivibrator 18-2 and the output signals of the multivibrator 14-2, 16-2, 16-2, and 18-2, each of which has an output pulse width of 800 ns. Correspondingly comprises a multiplexing (multiplexing) multiplexer 20 for outputting a frequency divider 12. As shown in this configuration, each multivibrator was implemented with SN74LS123 disclosed in the '85 bipolar digital integrated circuit data book, and the multiplexer was implemented with SN74LS153.

Specifically, the multi-vibrators 14-1, 16-1, and 18-1 of the first stage in the frequency divider control circuit 10 have a period of 1.544 MHz (this is 648 ns) and 2.048 MHz with respect to the reference clocks REF0, REF1, and REF2. The output pulse width is between one period of (which is 488ns). In addition, the second stage multivibrators 14-2, 16-2, and 18-2 have an output pulse width larger than one period of 1.544 MHz. The multiplexer 20 receives the clock information of the multi-vibrator 14-2, 16-2, and 18-2 of the second stage, and selects and outputs one of the clock information corresponding to the signal output from the selection circuit 8. .

Referring to FIG. 4, a method of determining a frequency divider based on an output characteristic of each multivibrator corresponding to a reference clock according to the configuration of FIG. 3 is as follows. 4 is a diagram illustrating the output waveforms of the division control circuit 10 for 1.544 MHz, and FIG. 4b is a diagram showing the output waveforms of the division control circuit 10 for 2.048 MHz. . First, as shown in FIG. 4A, for example, the reference clock REF0 is input at 1.544 MHz. At this time, since the output pulse width of the multi-vibrator 14-1 of the first stage is shorter than one period of the reference clock REF0, the multi-vibrator 14-2 of the second stage becomes a logic high. For example, as shown in FIG. 4B, the reference clock REF0 is input at 2.048 MHz. At this time, since the output pulse width of the multi-vibrator 14-1 of the first stage is longer than one period of the reference clock REF0, the multi-vibrator 14-2 of the second stage becomes a logic low. The same process is performed in the case of the reference clocks REF1 and REF2 and the multi-vibrator of the first stage and the multi-vibrator of the second stage that input them to the reference clocks. In this way, when the reference clock is input at 1.544 MHz, the output of the second stage multivibrator goes high, and when the reference clock is input at 2.048 MHz, the output of the second stage multivibrator goes low. It can be mixed regardless of 1.544MHz or 2.048MHz, from which it automatically adjusts the counter value in the divider circuit 12. In addition, even if three reference clocks REF0, REF1, and REF2 are mixed and input at 1.544 MHz and 2.048 MHz, they can all be accommodated. As a result, the dividing control circuit 10 according to the present invention automatically adapts the reference clock dividing determination circuit for the digital transmission of FIG. 2 to both the TI network and the EI network.

As described above, the reference clock frequency division decision circuit for digital transmission according to the present invention accommodates the reference clocks having different frequencies (1.544 MHz and 2.048 MHz) even if they are mixed and input at the same time. By dividing and outputting), it is possible to realize a digital transmission circuit in which each frame is automatically changed without forcibly changing the counter values of the division circuits in two communication networks having different channels. In addition, by automatically determining the necessary dispensing according to the input frequency, the inconvenience of having to recognize information about the input frequency in advance occurs.

Claims (2)

A digital transmission circuit comprising: a selection circuit for inputting a plurality of reference clocks having different frequencies and selecting one of the highest clocks having a good state among the inputs; and a predetermined division of the reference clock selected by the selection circuit according to the frequency. A first stage multivibrator for generating a synchronous loop external reference clock, a first stage multivibrator for inputting the plurality of reference clocks to output a signal having a first pulse width, and a second pulse for inputting an output of the first stage multivibrator; And a second stage multivibrator for outputting a signal having a width, and a multiplexing control circuit configured to select one of the outputs of the second stage multivibrator according to the reference clock selected by the selection circuit and to transfer the signal to the frequency divider circuit. A reference clock division determination circuit for digital transmission. The method of claim 1, wherein the first pulse width is a pulse width between one period of the first frequency and one period of the second frequency, the second pulse width is configured to be larger than one period of the first frequency A reference clock division determination circuit for digital transmission.