JP2621769B2 - DPLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DPLL for identifying received burst data signals arriving from a plurality of transmission circuits.
Circuit.

[0002]

2. Description of the Related Art An optical communication system using an optical fiber having excellent features such as low loss property and wide band property has been introduced mainly for a backbone system of a public communication network, and has a long distance of 2.4 Gbit / s. Large capacity systems (2.4 Gb / s new synchronous optical transmission system) have already been put into practical use.

[0003] In recent years, with the development of such optical transmission technology, with the aim of providing broadband communication services,
Research and development on optical subscriber transmission systems are underway. In such an optical subscriber transmission system, for example, as shown in FIG. 3, a plurality of slave stations 32, 33, and 34 are connected to an optical star coupler 31 in one master station 30 in order to reduce the cost of an optical communication system. , A passive double star (PDS) configuration connected by optical fibers 35, 36, 37, and 38 is being studied.

In this configuration, data signals from the transmitters of a plurality of slave stations arrive at the master station in a burst manner without bit synchronization. For this reason, in an actual burst data signal sequence, a preamble signal for synchronizing bits is generally added before the data signal. However, since the increase in the number of bits of the preamble signal decreases the transmission efficiency of the data signal, a circuit that performs timing extraction from such a received burst data signal can synchronize with a preamble signal having a small number of bits. High-speed synchronization characteristics are required. Further, in the PDS configuration of FIG. 3, since not all slave stations perform communication in the assigned time slots, a zero-bit continuation of a long bit number may occur in the master station. Therefore, the timing extraction circuit is also required to have a "tolerance characteristic for a long number of consecutive zero-sign bits".

Here, in a timing circuit applied to a long-distance transmission system, a tank circuit such as a SAW filter is frequently used.
Since there is a trade-off relationship between the two required characteristics, that is, the "tolerance characteristic of long bits to zero-code continuation", it is difficult to achieve both required characteristics. For this reason, in an optical subscriber transmission system such as a PDS configuration, a DPLL circuit composed of digital elements such as a counter and a selector is being studied in order to satisfy two required characteristics.

FIG. 2 shows a conventional example of a DPLL circuit described in Japanese Patent Application No. 05-128555. Conventional D of FIG.
In the PLL circuit, the received burst data signals arriving from the transmission circuits of the plurality of slave stations are delayed using the shift register 20 operated by the high-speed clock signal, and are converted into multi-phase burst data signals. The multi-phase burst data signal output from the shift register 20 is input to the selector circuit 21. Also, DPL
The clock signal input to the L circuit is input to the up / down counter 23 and the data identification circuit 24, and is output from the DPLL circuit as a clock signal.

On the other hand, a burst data signal of one phase selected by the selector circuit 21 is input to a clock terminal of the up / down counter 23, and a clock signal is input to an up / down control terminal. In the up / down counter 23 to which such a signal is input, the counter is incremented by +1 or -1 depending on the state ("H" or "L") of the clock signal at the transition point of the burst data signal. The value is input to the selector circuit 21.

Therefore, if the selector circuit 21 is controlled using the count signal from the up / down counter 23 so that the change point of the clock signal in the up / down counter 23 coincides with the change point of the burst data signal, a plurality of child Even when the received data signal from the transmitter of the station arrives in a burst state without bit synchronization, the phase relationship between the burst data signal and the clock signal input to the data identification circuit 24 is determined after the phase synchronization. Is almost constant. This makes it possible to output from the DPLL circuit an identification burst data signal for which data identification has always been performed in the data identification circuit 24 with an optimal phase relationship.

[0009]

In the conventional DPLL circuit, the count value of the up / down counter 23 is one.
The amount of phase control due to the change is fixed. In such a DPLL circuit, if the phase control amount is increased and the synchronization is established with a small number of up / down counts in order to satisfy the high-speed synchronization characteristic, if the phase fluctuation amount after the synchronization is large, the data discrimination is performed. The discrimination phase margin in the circuit 24 decreases, and the sensitivity deterioration amount increases. On the other hand, if the phase control amount is reduced to reduce the sensitivity deterioration amount, the number of up / down counts for establishing synchronization increases, so that the synchronization characteristics deteriorate. That is, the conventional DPL
The L circuit has a problem that a high-speed synchronization characteristic and a low sensitivity deterioration amount have a trade-off relationship.

If noise or the like is mixed in after the phase synchronization is performed, the up-down counter 2
Since the change in the count value of 3 directly affects the selector circuit 21, the phase control operation becomes unstable.

An object of the present invention is to solve such conventional problems, to achieve both high-speed synchronization characteristics and low sensitivity degradation, and to maintain the stability of the phase control operation after phase synchronization.

[0012]

In order to solve the above-mentioned problems, a means provided by the present invention is to provide a DPLL circuit for identifying a received burst data signal, wherein the received burst data signal is converted using a high-speed clock signal. Delay,
A shift register that generates a multi-phase burst data signal, a selector circuit that selects a single-phase burst data signal from the multi-phase burst data signal generated in the shift register, and a shift register that is selected by the selector circuit. A data identification circuit for identifying a burst data signal of one phase using a clock signal, a timer for measuring a predetermined time after a burst reset signal input in synchronization with the received burst data signal and outputting a timer signal; Comparing the phase relationship between the one-phase burst data signal output from the selector circuit and the clock signal, and synchronizing the one-phase burst data signal output from the selector circuit with the clock signal. A phase comparison / control circuit that outputs a control signal, and the timer signal Phase control signal from the comparator and control circuit is shifted bit by bit, characterized in that it is composed of a shift circuit for outputting to said selector circuit.

[0013]

According to the present invention, the count signal output from the up / down counter used as the phase comparison / control circuit and controlling the selector circuit is shifted bit by bit using a timer and a shift circuit. As a result, a large amount of phase control is performed until synchronization, and a small amount of phase control is performed after synchronization, so that both high-speed synchronization characteristics and low sensitivity degradation can be achieved.

Further, it is possible to remove the instability of the phase control operation after phase synchronization when noise or the like is mixed.

[0015]

FIG. 1 shows an embodiment of the present invention. The operation of the DPLL circuit of the present invention will be described with reference to FIG.

In the DPLL circuit of FIG. 1, the received burst data signals arriving from the transmission circuits of a plurality of slave stations are delayed by using a shift register 10 operated by a high-speed clock signal, and converted into multi-phase burst data signals. Is done. Then, the multi-phase burst data signal output from the shift register 10 is input to the selector circuit 11. The clock signal input to the DPLL circuit is input to the up / down counter 13 and the data identification circuit 14, and is output from the DPLL circuit as a clock signal.

On the other hand, a burst data signal of one phase selected by the selector circuit 11 is input to the clock terminal of the up / down counter 13, and a clock signal is input to the up / down control terminal. In the up / down counter 13 to which such a signal is input, the counter is incremented by +1 or -1 depending on the state of the clock signal ("H" or "L") at the change point of the burst data signal. The value is input to the shift circuit 15.

The operation of the shift circuit 15 before and after phase synchronization is different. This operation is illustrated in FIG.
This will be described with reference to FIG.

First, before the phase synchronization, the control signal from the up / down counter 13 is shifted to the upper bits one bit at a time, and "L" is output from the least significant bit. Thus, when the count value of the up / down counter 13 changes by ± 1, the output of the shift circuit 15 changes by ± 2. Therefore, in the selector circuit 11, the multi-phase data signal from the shift register 10 is selected every other phase, so that the amount of phase control is equivalently doubled. After the phase synchronization, as shown in (1) after the phase synchronization in FIG. 4, the control signal from the up / down counter 13 is shifted one bit at a time from the state before the phase synchronization to lower bits. This allows
The count value of the up / down counter 13 becomes the output value of the shift circuit 15 as it is, and the selector circuit 11 selects the multiphase data signals one by one in order. As described above, a data signal having a large phase control amount can be used until synchronization, and a data signal having a smaller phase control amount than before synchronization can be used after synchronization.

Here, the switching in the shift circuit 15 is performed as follows, for example. First, after the timer 16 is reset by a burst reset signal input in synchronization with the reception burst data signal, the reception burst data signal is reduced to the number of preamble bits necessary for synchronization using the data signal of a large phase control amount. Count the number of bits. Then, when the set count is reached, a control signal (“H” signal in FIG. 4) is output from the timer 16, and the shift circuit 15 is switched using the control signal to reduce the phase control amount. In addition,
When the phase control amount is switched by the shift circuit 15, the control signal output from the timer 16 is also supplied to the preset terminal of the up / down counter 13 so that the polyphase data signal selected by the selector circuit 11 does not change. Input and shifted by a shift circuit 15 , for example, a selector circuit
Control signal similar to the control signal output to
Input to the preset value setting terminal of the down counter 13 and
The feedback from the timer 16
Immediately after the control signal is input and switching is performed, this preset
It is possible to output the cut value to the shift circuit 15.
Thereby, in the state (1) after the phase synchronization of FIG.
Also, the data signal selected before the switching of the shift circuit 15 is selected immediately after the switching. here,
Since the signal input to the CLK terminal of the timer 16 only needs to be synchronized with the received burst data signal, the burst data signal output from the selector circuit 11 may be used.

As described above, the selector circuit 11 is switched via the shift circuit 15 using the count signal from the up / down counter 13 so that the change point of the clock signal in the up / down counter 13 coincides with the change point of the burst data signal. By controlling the DPL of this configuration,
Received data signals from transmitters of a plurality of slave stations are sent to the L circuit,
Even when the signals arrive in a burst without synchronization, the phase relationship between the burst data signal and the clock signal input to the data identification circuit 14 becomes substantially constant after the phase synchronization. Therefore, the data identification circuit 14
It is possible to output from the DPLL circuit an identification burst data signal in which data identification has always been performed with an optimum phase relationship.

That is, in the present invention, in order to solve the above-described problem, the count signal output from the up / down counter 13 and controlling the selector circuit 11 is shifted in bit units using the timer 16 and the shift circuit 15. Therefore, a large amount of phase control is performed until synchronization, and a small amount of phase control is performed after synchronization. Thus, it is possible to achieve both high-speed synchronization characteristics and low sensitivity degradation.

If noise or the like is mixed in after the phase synchronization, a change in the count value of the up / down counter 13 due to the noise directly affects the selector circuit 11, and the phase control operation may become unstable. But,
In this case, the shift operation after the phase synchronization of the shift circuit 15 is, for example, as shown in (2) after the phase synchronization in FIG.
Bits are shifted bit by bit so that “L” is output from the most significant bit. As a result, the count value of the up / down counter 13 is reduced by half on the selector circuit 11 side.
Can be reduced to the count value. Therefore,
The amount of change in the count value of the up / down counter 13 can be compressed using the shift circuit 15, and the instability of the phase control operation when noise or the like is mixed can be eliminated. In this operation, the shift circuit 15
When the phase control amount is switched by the
Prevent changes in the selected polyphase data signal
Control signal output from the timer 16
Input to the preset terminal of the counter 13
The data is shifted by the shift circuit 15 and output to the selector circuit 11.
Control signal similar to the control signal
Feed as input to the preset value setting terminal of
If it is backed up, the control signal from the timer 16 will be input
Immediately after switching, this preset value is shifted.
To the output circuit 15. This allows
Even in the state (2) after the phase synchronization of FIG.
The data signal selected before switching of 15 switches
Immediately after that is selected.

Note that, instead of the up / down counter 13, a circuit whose value changes at a change point of the data signal from the selector circuit 11 depending on whether the state of the clock signal is "H" or "L", For example, a similar effect can be obtained by using a shift register or the like.

Also, since the timer 16 only needs to output the control signal a predetermined time after the burst reset signal is input, not only a configuration for counting the received burst data signal but also a mono-multi circuit may be used. .

[0026]

As described above, according to the present invention, the count signal for controlling the selector circuit, which is output from the up / down counter used as the phase comparison / control circuit,
Since the shift is performed in units of bits using a timer and a shift circuit, a large amount of phase control is required until synchronization, and a small amount of phase control is required after synchronization, thus achieving both high-speed synchronization characteristics and low sensitivity degradation. It becomes possible.

Further, by changing the shift amount in the shift circuit after the phase synchronization, it is possible to eliminate the instability of the phase control operation when noise or the like is mixed.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a PLL circuit of the present invention.

FIG. 2 is a diagram showing one embodiment of a conventional DPLL circuit.

FIG. 3 is a diagram showing an example of a passive double star configuration.

FIG. 4 illustrates an example of an operation of a shift circuit.

[Explanation of symbols]

 10, 20 shift register, 11, 21 selector circuit, 13, 23 up / down counter, 14, 24 data identification circuit, 15 shift circuit, 16 timer, 17, 25 DPLL circuit, 30 master station, 31 optical star coupler, 32, 33, 34 slave station, 35, 36, 37, 38 Optical fiber.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04B 10/28 H04L 12/44

Claims (1)

(57) [Claims] 1. A DPLL circuit for identifying a received burst data signal, comprising: a shift register for delaying the received burst data signal using a high-speed clock signal to generate a multi-phase burst data signal; A selector circuit for selecting a burst data signal of one phase from the multi-phase burst data signals obtained, and a data identification circuit for identifying the burst data signal of the one phase selected by the selector circuit using a clock signal A timer that measures a predetermined time after a burst reset signal input in synchronization with the received burst data signal and outputs a timer signal; a one-phase burst data signal output from the selector circuit and the clock Compare the phase relationship of the signals, and output from the selector circuit. A phase comparison / control circuit for outputting a control signal for synchronizing a phase of the burst data signal with the clock signal; and shifting the control signal from the phase comparison / control circuit in units of bits by the timer signal. A DP comprising a shift circuit for outputting to the selector circuit.
LL circuit.