KR0141293B1 - Data Clock Signal Generation Circuit - Google Patents

Abstract

This data clock signal generation circuit is for generating a data clock signal provided from the IOM2 bus to a signal suitable for voice information processing by the ADPCM method which is performed at the radio base station and the handset. To this end, the circuit comprises: a first clear signal generator for generating a clear signal in synchronization with a frame synchronization signal: a first counter for clearing the first clear signal generator and a clock signal output from the oscillator, a data clock A detector which counts signals and detects the maximum number of processed bits per second to be processed by the voice coding method of the radio base station. Stored buffer: A second counter that is cleared at the edge of the data clock signal and counts the high frequency clock signal output from the oscillator. Comparator that compares the output signal of the buffer with the output value of the second counter. Flip-flop to generate the data clock signal adjusted by the output signal of It is configured to include.

Description

Data Clock Signal Generation Circuit

1 is a data clock signal generation circuit diagram according to the present invention;

FIG. 2 is a timing diagram of a part of the circuit diagram shown in FIG.

* Explanation of symbols for main parts of the drawings

100: IOM2 bus unit 110: first high speed clear signal generator

120: oscillator 130: second high speed clear signal generation unit

140: third high speed clear signal generation unit 150: counting means

160: buffer 170: DCL detection unit

180: fourth counter 190: comparator

200: flip flop

The present invention relates to a connection device between a DECT (Digital European Codeless Telecommunication) wireless base station and an Integrated Services Digital Network (ISDN) switch, and in particular, an ISDN Oriented Modulo It relates to a circuit for generating a data clock signal (DATA CLOCK, hereinafter referred to as DCL) used in an IOM2 bus having a period suitable for use in a wireless base station and a handset.

Dect-based radio base stations are fixed stations that employ a personal mobile communication system as defined by the European Telecommunications Standards Committee, and use the IOM2 bus for communication between ISDN exchanges and handsets (or terminals). IOM2 bus is composed of frame synchronization signal (Frame SYNC: FSC), data clock signal (Data Clock: DCL), uplink data (DUP) and downlink data (Data Down: DDP). The clock signal is generated, and the DCL generates 192 clock signals in one frame. Two data clocks are used for one data transmission of uplink data and downlink data. It is possible to send and receive.

These IOM2 buses are designed based on ISDN exchanges, which generate data clock signals so that 64K bits per second are transmitted when processing voice information (since ISDN exchanges process voice signals using pulse code modulation (PCM)). . However, between the base station and the handset, and inside the handset, the IOM2 is compressed twice as much as the ISDN switch because it processes 32K bits per second by the adaptive pulse code modulation (ADPCM). It is difficult to use the data clock signal provided from the bus as it is for the radio base station and the handset.

Accordingly, an object of the present invention is to generate a data clock signal generated on the IOM2 bus twice as fast as a data clock signal provided on the IOM2 bus to a signal suitable for voice information processing by the ADPCM method performed at the wireless base station and the handset. To provide a data clock signal generation circuit for.

In order to achieve the above object, a circuit according to the present invention is a modular IOM2 connection system for generating a frame synchronization signal (FSC) and a data clock signal (DLC) for data transmission and reception with a general information communication network switch or terminal. A circuit for generating a data clock signal suitable for a voice coding method performed by a radio base station having a bus unit and an oscillator generating a high frequency clock signal, the signal synchronization being synchronized with the frame synchronization signal and the high frequency clock signal output from the oscillator. A first clear signal generator for generating a clear signal: A first counter for counting clock signals cleared by the first clear signal generator and output from the oscillator: To a signal output from the first clear signal generator. Cleared by the user, counting the data clock signal, and the voice coding room of the wireless base station. Detecting unit for detecting the maximum number of processing bits per second to be processed by the buffer: Temporarily storing a value corresponding to a quarter period of the data clock signal applied from the first counter in synchronization with the output signal of the detection unit: A buffer of the data clock signal A second counter for counting the high frequency clock signal cleared at the edge and output from the oscillator. A comparator for detecting a point having the same value by comparing the output signal of the buffer and the output value of the second counter. An edge signal for the data clock signal. And a flip-flop for generating a data clock signal, which is reset by and is adjusted by the output signal of the comparator and adjusted to be suitable for the voice coding scheme.

Next, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates an embodiment of a data clock signal generation circuit according to the present invention, and includes a frame synchronization signal FSC and an oscillator output from an IOM2 bus unit 100, an oscillator 120, and an IOM2 bus unit 100. The first high speed clear signal generation unit 110 and the data clock signal DCL output from the IOM2 bus unit 100 and the oscillator 120 to generate a clear signal in synchronization with the high frequency clock signal output from the 120. The second high speed clear signal generation unit 130 for generating a clear signal in synchronization with the high frequency clock signal to be cleared in synchronization with the high frequency clock signal output from the reverse phase signal (/ DCL) of the data clock signal and the oscillator 120 The data clock is generated by signals output from the third high speed clear signal generation unit 130, the second high speed clear signal generation unit 130, and the third high speed clear signal generation unit 140 for generating a signal. Signal (DCL) or the edge detection unit (G4) for detecting whether the polling of the reverse phase of the data clock signal (/ DCL). The counting means 150 for counting the signal cleared by the signal output from the first high speed clear signal generating unit 110 and output from the oscillator 120 and the DCL signal output from the IOM2 bus unit 100 are counted. To temporarily store the number of high frequency clock signals corresponding to a quarter cycle of the DCL cycle among the values counted by the DCL detector 170 and the DCL detector 170 to detect the 32nd DCL signal A fourth counter 180 for counting a high frequency clock signal cleared by the buffer 160 and an edge detector G4 and output from the oscillator 120, a signal output from the buffer 160, and a fourth counter 180. Comparator 190 for comparing the signal output from the (). It is configured as a flip-flop 200 for outputting a DCL signal which is preset (/ PR) by the signal output from the comparator 190 and reset (/ RESET) by the signal output from the edge detector (G4) and adjusted. do. 2 is an operation timing diagram of a portion shown in FIG.

Then, an embodiment according to the present invention will be described in detail with reference to FIGS. 1 and 2.

First, the IOM2 bus unit 100 includes an IOM2 bus master controller 101 and a slave controller 102, and separates data received from an exchanger, not shown, into D and B channels, respectively. Downlink processing may be performed to an unillustrated terminal or another device in a wireless base station, or data from a non-illustrated terminal or another device of a radio base station may be uplinked to a non-illustrated exchange. As described above, the IOM2 bus unit 100 includes a frame synchronization signal (hereinafter referred to as FSC), a data clock signal (hereinafter referred to as DLC), an uplink transmission data (DUP), and a downlink transmission data (DOP) transmission line. .

The first fast-clear signal generating unit 110 is composed of three D-flop flops 111, 112, and 113, two buffers 81 and 82, and an AND logic device G2, and an IOM2 bus. The PSC signal output from the unit 100 and the high frequency clock signal output from the oscillator 120 to be described later are generated as clear signals of the count means 150 and the DCL detector 170 to be described later.

That is, the FSC signal generated when the data transfer of the IOM2 bus unit 100 starts is performed by the clock terminal of the D flip-flop 111 having the highest potential Vcc connected to the input terminal D and the preset terminal / PR. Is applied to (CLK). The D flip-flop 111 outputs a high logic signal through the output terminal Q at the rising edge of the FSC signal generated at the 125usec cycle as described above, and outputs low logic to the inverted output terminal / Q. do. The signal output through the output terminal Q of the D flip flop 111 is transmitted to the input terminal D of the D flip flop 112 connected to the next stage. The D flip-flop 112 transmits the high logic level applied to the D input terminal to the input terminal D of the next D flip flop 113 in synchronization with the rising edge of the clock signal output from the oscillator 120. The D flip-flop 113 also outputs a high logic state signal for the signal applied to the input terminal D in synchronization with the clock signal output from the oscillator 120, but here the inverted output of the D flip-flop 113 has a low logic state. Only the signal / Q is transmitted to the buffer B1. The low logic state signal transmitted to the buffer B1 is applied to one input terminal of the logical multiplication device G1 through the buffer 52. The logical multiplication device G1 is a reset (/ RESET) signal and the buffer 32. Multiplying the output signal of < RTI ID = 0.0 >) < / RTI > The two D flip-flops 112. 113 and the buffers B1. B2 used here are cleared of the count means 150 and the DCL detector 170 as described above in which the D flip-flop 111 is synchronized with the FSC signal. After outputting the signal, the delay time is reset. Here, the inverted output signal (/ Q) of the D flip-flop 111 is provided as a clear signal of the counting means 150 and the DCL detector 170 described later.

The oscillator 120 generates a high frequency clock signal and is configured in the same manner as in the prior art.

The counting means 150 includes a first counter 151 and a second counter 152, and counts the high frequency clock signal OSC provided by the oscillator 120 as shown in FIG. The clear state is controlled by the signal output from the clear signal generator 110. That is, the first and second counters 151 and 152 are configured as 8-bit counters, and the oscillator 120 uses the most significant output bit Q7 of the second counter 152 as the clock signal of the first counter 151. By counting the clock signal applied from, it can be replaced by one 16-bit counter. The counted value is cleared by the clear signal provided by the first fast clear signal generator 110, and the counted value is transmitted to the buffer 160.

The DCL detector 170 is composed of an 8-bit third counter 171, a plurality of inverters IN2 to 8, and a multiplier element G5 to generate a DCL generated from the IOM2 bus unit 100 for the 32nd time. To detect. In this case, the 32nd generation of DCL is detected because the current voice coding scheme used in the wireless base station and the handset is configured to transmit 32 K bits of data per second. The number of DCLs detected when the processing bits per second changes can be set differently.

That is, the third counter 171 counts the DCL output from the IOM2 bus unit 100 while the clear state is controlled by the signal output from the first high speed clear signal generation unit 110. The counted result is transmitted to the inverters IN2 to 8 and the logical multiplication device G5 connected to the next stage.

The inverters IN2 to 8 and the logical product G5 output a high logic signal to the clock terminal CLK of the buffer 160 to be described later when the count value output from the third counter 171 becomes 32. It is made up of logical structure.

The buffer 160 is connected to the D1 to D7 input terminals of the input terminals D0 to D7 to the Q0 to 6 output terminals of the first counter 151 in the counting means 150, and the D0 input terminal is connected to the second counter 152. 8-bit D flip-flop connected to the Q7 output terminal and reset by a reset signal (/ RESET) provided from a central processing unit (CPU) (not shown). The count value provided by the means 150 is temporarily stored and then transmitted to one input terminal A of the comparator 190 to be described later. At this time, the count value provided by the counting means 150 is the number of high frequency clock signals corresponding to a quarter period of the DCL applied as the second (B) diagram.

Meanwhile, the second fast clear signal generator 130 has the same structure as the first fast clear signal generator 110 and generates the fast clear signal for the DCL signal output from the IOM2 bus unit 100. It is to.

That is, in order to generate the clear signal, the second high speed clear signal generation unit 130 provides the clock terminal CLK of the D flip-flop 131 when the DCL signal is output from the IOM2 bus unit 100. The D flip-flop 131 outputs a high logic level equal to the second (C) degree at the rising edge of the DCL signal applied through the clock terminal at the same period as the second (A) degree, and is returned by the logical product element G3. Is set. The logical multiplication device G3 generates a D flip-flop 131 in synchronization with a reset signal (/ RESET) provided from a CPU (not shown) and a high frequency clock signal generated by the second (A) degree in the oscillator 130. The output signal Q is logically multiplied by the signal applied via the two D flip-flops 132 and 133 and the buffers B3 and B4. The number of D flip-flops used here may be adjusted according to the processing time, and the high speed clear signal output from the D flip-flop 131 is transmitted to the edge detector G4, which will be described later.

The third high speed clear signal generation unit 140 is configured by adding the inverter IN1 to the same structure as the first and second high speed clear signal generation units 110 and 130 described above, and thus the second high speed clear signal generation unit 130. This is for generating a clear signal having a reverse phase with the clear signal generated in the < RTI ID = 0.0 > That is, when a DCL clock signal such as the second (A) diagram is applied from the IOM2 bus unit 100, the clock terminal CLK of the D pull-flop 141 is inverted through the inverter IN1 as shown in the second (D) diagram. To send). The D flip-flop 141 outputs the signal converted to the high logic level as shown in the second (E) at the rising edge of the clock signal inverted and applied as shown in the second (D) through the output terminal (Q). The output signal is generated by the logical multiplication device G3 via the D flip-flops 142 and 143 and the buffers B5 and B6 provided at the next stage as in the high speed clear signal generating unit 110 and 130 described above. Logically multiplies the reset signal / RESET provided from the CPU (not shown) to reset the D flip-flops 141, 142, and 143 in the third high speed clear signal generation unit 140. . The high speed clear signal output from the inverted output terminal / Q of the D flip-flop 141 is transmitted to the edge detector G4.

The edge detector 04 is composed of a logic element and outputs the output signal of the second high speed clear signal generator 130 such as the second (C) diagram and the third high speed clear signal generator 140 of the second (E) diagram. The output signal is logically summed and output as shown in the second (F) diagram. The output signal is transmitted to the clear terminal (/ CLR) of the fourth counter 180 and the reset terminal (/ RES) of the flip-flop 200 to be described later.

The fourth counter 180 includes an 8-bit counter. When the clear state is controlled by the signal output from the edge detector G4 as shown in FIG. 2F, the fourth counter 180 counts the clock signal output from the oscillator 120, and counts. The converted value is output as 8 bit data. The output 8-bit data is transmitted to one input terminal B of the comparator 190.

The comparator 190 compares the 8-bit data value applied from the buffer 160 with the data value output from the fourth counter 180 and outputs a high logic level when they match each other. The output is like a tile. The output signal is transmitted to the preset terminal (/ PR) of the flip-flop 200.

The flip-flop 200 is composed of a D-type flip-flop having the highest potential Vcc connected to the input terminal D and the clock terminal CLK, and reset by the signal output from the edge detector G4. A DCL signal preset by the signal output from 190 and adjusted as shown in FIG. 2G is output. As shown in FIG. 2G, the final DCL signal output from the flip-flop 200 is 32K per second. The bit is generated twice as fast as the third (8) degree output from the IOM2 bus unit 100 and a DCL having a red period so that the bit can be processed.

As described above, the present invention can provide a data clock signal suitable for the voice coding method used in the radio base station and the terminal by generating the data clock signal (DCL) used in the IOM2 bus by double the speed.

Claims (4)

Comprehensive information network connection type modular (IOM2) bus unit for generating frame synchronization signal (FSC) and data clock signal (DLC) for transmitting / receiving data to / from a general information communication network switch or terminal and an oscillator for generating a high frequency clock signal A circuit for generating a data clock signal suitable for a voice coding scheme performed at a wireless base station, the circuit comprising: a first clear signal generator for generating a clear signal in synchronization with the frame synchronization signal and the high frequency clock signal output from the oscillator A first counter cleared by the first clear signal generator and counted by a signal output from the oscillator, a first counter cleared by a signal output from the first clear signal generator, and counting the data clock signal In the voice coding scheme of the wireless base station. A detector for detecting the maximum number of processing bits per second: A buffer for temporarily storing a value corresponding to a quarter period of the data clock signal applied from the first counter in synchronization with an output signal of the detector: The data clock signal A second counter for counting the high frequency clock signal cleared at the edge of the second oscillator; a comparator for detecting a point having the same value by comparing an output value of the buffer and an output value of the second counter: the data And a flip-flop for generating a data clock signal that is reset by an edge signal to a clock signal and preset by an output signal of the comparator and adapted to fit the voice coding scheme. Circuit. 2. The second clear signal generator of claim 1, wherein the data clock signal generation circuit is configured to generate a clear signal in synchronization with the data clock signal output from the IOM2 bus unit and the high frequency clock signal output from the oscillator. A third clear signal generator configured to generate a clear signal in synchronization with an antiphase signal of the data clock signal and the high frequency clock signal: performing a logical sum of the signals output from the first clear signal generator and the second clear signal generator And an edge detector for detecting the edge. The data clock signal generating circuit according to claim 1 or 2, wherein the maximum number of processed bits per second in the detector corresponds to 32 bits. 3. The data clock signal generation circuit according to claim 1 or 2, wherein the flip-flop is a D-type flip flop fixedly connected to a data input terminal and a clock signal input terminal.