KR960043116A - Planarization method of semiconductor device - Google Patents
Planarization method of semiconductor device Download PDFInfo
- Publication number
- KR960043116A KR960043116A KR1019950011921A KR19950011921A KR960043116A KR 960043116 A KR960043116 A KR 960043116A KR 1019950011921 A KR1019950011921 A KR 1019950011921A KR 19950011921 A KR19950011921 A KR 19950011921A KR 960043116 A KR960043116 A KR 960043116A
- Authority
- KR
- South Korea
- Prior art keywords
- photoresist film
- film
- semiconductor device
- planarization
- spin
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims abstract 4
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract 9
- 239000002184 metal Substances 0.000 claims abstract 4
- 239000011521 glass Substances 0.000 claims abstract 3
- 238000005530 etching Methods 0.000 claims abstract 2
- 239000011229 interlayer Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 간단한 공정을 통해 국부 평탄화는 물론 광영 평탄화를 동시에 이룰 수 있는 반도체 소자의 평탄화 방법에 관한 것으로, 상층 금속막 형성후 층간절연막, 스핀 온 클래스막, 감광막을 차례로 형성하는 단계; 블랫킹 노광 및 현상공정을 통해 상기 감광막을 일정정도 제거하되, 스테퍼의 초점 위치를 조절하여 상대적으로 높은 토폴로지에 위치하는 감광막을 부분적으로 제거하는 단계; 잔류하는 상기감광막을 제거하고, 에치백공정을 통해 상기 스핀 온 글래스막을 식각하여 상기 상층 금속막을 노출시키는 단계; 잔류하는 상기 감광막 제거후 전체 상부에 절연층을 형성하여 평탄화하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a planarization method of a semiconductor device capable of simultaneously performing local planarization and photolithographic planarization through a simple process. Removing the photoresist film to a certain degree through a blacking exposure and developing process, and partially removing the photoresist film positioned in a relatively high topology by adjusting a focal position of the stepper; Removing the remaining photoresist layer and etching the spin-on glass layer through an etch back process to expose the upper metal layer; And removing the remaining photoresist film to form an insulating layer over the entire upper portion of the photoresist film.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1B도 내지 제1C도는 본 발명의 일실시예에 따른 평탄화 과정을 나타내는 단면도.1B to 1C are cross-sectional views showing a planarization process according to an embodiment of the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950011921A KR960043116A (en) | 1995-05-15 | 1995-05-15 | Planarization method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950011921A KR960043116A (en) | 1995-05-15 | 1995-05-15 | Planarization method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR960043116A true KR960043116A (en) | 1996-12-23 |
Family
ID=66523487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950011921A KR960043116A (en) | 1995-05-15 | 1995-05-15 | Planarization method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR960043116A (en) |
-
1995
- 1995-05-15 KR KR1019950011921A patent/KR960043116A/en not_active Application Discontinuation
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19950515 |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |