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KR970053558A - Method for forming interlayer insulating film of semiconductor device - Google Patents

Method for forming interlayer insulating film of semiconductor device Download PDF

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Publication number
KR970053558A
KR970053558A KR1019950065695A KR19950065695A KR970053558A KR 970053558 A KR970053558 A KR 970053558A KR 1019950065695 A KR1019950065695 A KR 1019950065695A KR 19950065695 A KR19950065695 A KR 19950065695A KR 970053558 A KR970053558 A KR 970053558A
Authority
KR
South Korea
Prior art keywords
interlayer insulating
film
insulating film
forming
semiconductor device
Prior art date
Application number
KR1019950065695A
Other languages
Korean (ko)
Inventor
박윤수
김천수
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950065695A priority Critical patent/KR970053558A/en
Publication of KR970053558A publication Critical patent/KR970053558A/en

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 반도체 소자의 금속층간 절연막 형성 방법에 관한 것으로, 절연 특성 및 표면의 평판도를 향상시키기 위하여 제1층간 절연막을 형성한 후 금속 패턴의 사이에 SOG막을 매립시켜 단차를 감소시키고 전체면에 제2및 제3층간 절연막을 형성하므로써 상기 SOG막의 노출로 인한 불량의 발생을 방지하며, 표면의 평탄도를 향상시킬 수 있다. 그러므로 소자의 전기적 특성 및 신뢰성이 향상될 수 있는 반도체 소자의 금속층간 절연막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film of a semiconductor device. In order to improve insulating properties and surface flatness, a first interlayer insulating film is formed, and a SOG film is buried between the metal patterns to reduce the step and reduce the level. By forming the second and third interlayer insulating films, the occurrence of defects due to the exposure of the SOG film can be prevented and the surface flatness can be improved. Therefore, the present invention relates to a method for forming an interlayer insulating film of a semiconductor device, which may improve electrical characteristics and reliability of the device.

Description

반도체 소자의 금속층간 절연막 형성 방법Method for forming interlayer insulating film of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2D도는 본 발명에 따른 반도체 소자의 금속층간 절연막 형성 방법을 설명하기 위한 소자의 단면도이다.2A to 2D are cross-sectional views of devices for explaining a method for forming an interlayer insulating film of a semiconductor device according to the present invention.

Claims (3)

반도체 소자의 금속층간 절연막 형성 방법에 있어서, 절연층이 형성된 실리콘 기판상에 하부 금속층을 형성하고 패터닝한 후 전체 상부면에 제1층간 절연막 및 SOG막을 순차적으로 형성하는 단계와, 상기 단계로부터 상기 제1층간 절연막이 노출되는 시점까지 상기 SOG막을 에치 백하여 표면을 평탄화시킨 후 전체 상부면에 감광막을 도포하고, 노출된 상기 제1층간 절연막상에만 상기 감광막이 잔류되도록 패터닝하는 단계와, 상기 단계로부터 상기 패터닝된 감광막을 마스크로 이용하여 상기 SOG막을 소정 깊이 삭각하는 단계와, 상기 단계로부터 상기 감광막을 제거한 후 전체 상부면에 제2및 제3층간 절연막을 순차적으로 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성 방법.A method of forming an interlayer insulating film of a semiconductor device, the method comprising: forming and patterning a lower metal layer on a silicon substrate on which an insulating layer is formed, and sequentially forming a first interlayer insulating film and an SOG film on an entire upper surface thereof; Etching back the SOG film to a point where the interlayer insulating film is exposed, planarizing the surface thereof, and then applying a photoresist film to the entire upper surface, and patterning the photoresist film to remain only on the exposed first interlayer insulating film; Cutting the SOG film by a predetermined depth using the patterned photosensitive film as a mask, and sequentially removing the photosensitive film from the step, and subsequently forming second and third interlayer insulating films on the entire upper surface thereof. A method of forming an interlayer insulating film of a semiconductor device. 제1항에 있어서, 상기 제2층간 절연막은 언도프 산화막인 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성 방법.The method of claim 1, wherein the second interlayer insulating film is an undoped oxide film. 제1항에 있어서, 상기 제3층간 절연막은 BPSG막인 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성 방법.The method of claim 1, wherein the third interlayer insulating film is a BPSG film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065695A 1995-12-29 1995-12-29 Method for forming interlayer insulating film of semiconductor device KR970053558A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950065695A KR970053558A (en) 1995-12-29 1995-12-29 Method for forming interlayer insulating film of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950065695A KR970053558A (en) 1995-12-29 1995-12-29 Method for forming interlayer insulating film of semiconductor device

Publications (1)

Publication Number Publication Date
KR970053558A true KR970053558A (en) 1997-07-31

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950065695A KR970053558A (en) 1995-12-29 1995-12-29 Method for forming interlayer insulating film of semiconductor device

Country Status (1)

Country Link
KR (1) KR970053558A (en)

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Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19951229

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid