KR960042974A - - Google Patents
Info
- Publication number
- KR960042974A KR960042974A KR19960018076A KR19960018076A KR960042974A KR 960042974 A KR960042974 A KR 960042974A KR 19960018076 A KR19960018076 A KR 19960018076A KR 19960018076 A KR19960018076 A KR 19960018076A KR 960042974 A KR960042974 A KR 960042974A
- Authority
- KR
- South Korea
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US44749095A | 1995-05-23 | 1995-05-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR960042974A true KR960042974A (ko) | 1996-12-21 |
Family
ID=23776586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR19960018076A Pending KR960042974A (ko) | 1995-05-23 | 1996-05-22 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6150252A (ko) |
| EP (1) | EP0793268A3 (ko) |
| JP (1) | JPH09223741A (ko) |
| KR (1) | KR960042974A (ko) |
| TW (1) | TW302513B (ko) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09115866A (ja) * | 1995-10-17 | 1997-05-02 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
| KR100440418B1 (ko) * | 1995-12-12 | 2004-10-20 | 텍사스 인스트루먼츠 인코포레이티드 | 저압,저온의반도체갭충전처리방법 |
| US6054379A (en) * | 1998-02-11 | 2000-04-25 | Applied Materials, Inc. | Method of depositing a low k dielectric with organo silane |
| US6143655A (en) | 1998-02-25 | 2000-11-07 | Micron Technology, Inc. | Methods and structures for silver interconnections in integrated circuits |
| US6121126A (en) * | 1998-02-25 | 2000-09-19 | Micron Technologies, Inc. | Methods and structures for metal interconnections in integrated circuits |
| US6492694B2 (en) | 1998-02-27 | 2002-12-10 | Micron Technology, Inc. | Highly conductive composite polysilicon gate for CMOS integrated circuits |
| US6815303B2 (en) * | 1998-04-29 | 2004-11-09 | Micron Technology, Inc. | Bipolar transistors with low-resistance emitter contacts |
| US6627539B1 (en) * | 1998-05-29 | 2003-09-30 | Newport Fab, Llc | Method of forming dual-damascene interconnect structures employing low-k dielectric materials |
| US5948467A (en) * | 1998-07-24 | 1999-09-07 | Sharp Laboratories Of America, Inc. | Enhanced CVD copper adhesion by two-step deposition process |
| JP2000106397A (ja) * | 1998-07-31 | 2000-04-11 | Sony Corp | 半導体装置における配線構造及びその形成方法 |
| TW439204B (en) * | 1998-09-18 | 2001-06-07 | Ibm | Improved-reliability damascene interconnects and process of manufacture |
| US6383915B1 (en) * | 1999-02-03 | 2002-05-07 | Applied Materials, Inc. | Tailoring of a wetting/barrier layer to reduce electromigration in an aluminum interconnect |
| US6486063B2 (en) * | 2000-03-02 | 2002-11-26 | Tokyo Electron Limited | Semiconductor device manufacturing method for a copper connection |
| US6723634B1 (en) * | 2002-03-14 | 2004-04-20 | Advanced Micro Devices, Inc. | Method of forming interconnects with improved barrier layer adhesion |
| US20050006770A1 (en) * | 2003-07-08 | 2005-01-13 | Valeriy Sukharev | Copper-low-K dual damascene interconnect with improved reliability |
| US7118801B2 (en) * | 2003-11-10 | 2006-10-10 | Gore Enterprise Holdings, Inc. | Aerogel/PTFE composite insulating material |
| US7101787B1 (en) | 2004-04-09 | 2006-09-05 | National Semiconductor Corporation | System and method for minimizing increases in via resistance by applying a nitrogen plasma after a titanium liner deposition |
| US7482266B2 (en) * | 2007-02-15 | 2009-01-27 | United Microelectronics Corp. | Method of forming composite opening and method of dual damascene process using the same |
| US7772123B2 (en) | 2008-06-06 | 2010-08-10 | Infineon Technologies Ag | Through substrate via semiconductor components |
| US8525343B2 (en) * | 2010-09-28 | 2013-09-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device with through-silicon via (TSV) and method of forming the same |
| US8901701B2 (en) * | 2011-02-10 | 2014-12-02 | Chia-Sheng Lin | Chip package and fabrication method thereof |
| US9685366B1 (en) | 2016-04-21 | 2017-06-20 | International Business Machines Corporation | Forming chamferless vias using thermally decomposable porefiller |
| US10998221B2 (en) | 2017-07-14 | 2021-05-04 | Micron Technology, Inc. | Semiconductor constructions having fluorocarbon material |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0199216A (ja) * | 1987-10-13 | 1989-04-18 | Fujitsu Ltd | 半導体装置の製造方法 |
| US5008216A (en) * | 1988-10-03 | 1991-04-16 | International Business Machines Corporation | Process for improved contact stud structure for semiconductor devices |
| JP2697796B2 (ja) * | 1988-11-14 | 1998-01-14 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
| EP0393381B1 (en) * | 1989-04-17 | 1995-11-08 | International Business Machines Corporation | Lamination method for coating the sidewall or filling a cavity in a substrate |
| US5073518A (en) * | 1989-11-27 | 1991-12-17 | Micron Technology, Inc. | Process to mechanically and plastically deform solid ductile metal to fill contacts of conductive channels with ductile metal and process for dry polishing excess metal from a semiconductor wafer |
| US5108951A (en) * | 1990-11-05 | 1992-04-28 | Sgs-Thomson Microelectronics, Inc. | Method for forming a metal contact |
| US5011793A (en) * | 1990-06-19 | 1991-04-30 | Nihon Shinku Gijutsu Kabushiki Kaisha | Vacuum deposition using pressurized reflow process |
| CA2061119C (en) * | 1991-04-19 | 1998-02-03 | Pei-Ing P. Lee | Method of depositing conductors in high aspect ratio apertures |
| GB9414145D0 (en) * | 1994-07-13 | 1994-08-31 | Electrotech Ltd | Forming a layer |
| ATE251342T1 (de) * | 1991-05-28 | 2003-10-15 | Trikon Technologies Ltd | Verfahren zum füllen eines hohraumes in einem substrat |
| TW520072U (en) * | 1991-07-08 | 2003-02-01 | Samsung Electronics Co Ltd | A semiconductor device having a multi-layer metal contact |
| JP2718842B2 (ja) * | 1991-07-17 | 1998-02-25 | シャープ株式会社 | 半導体集積回路用配線金属膜の製造方法 |
| EP0526889B1 (en) * | 1991-08-06 | 1997-05-07 | Nec Corporation | Method of depositing a metal or passivation fabric with high adhesion on an insulated semiconductor substrate |
| US5371042A (en) * | 1992-06-16 | 1994-12-06 | Applied Materials, Inc. | Method of filling contacts in semiconductor devices |
| US5288665A (en) * | 1992-08-12 | 1994-02-22 | Applied Materials, Inc. | Process for forming low resistance aluminum plug in via electrically connected to overlying patterned metal layer for integrated circuit structures |
| GB9224260D0 (en) * | 1992-11-19 | 1993-01-06 | Electrotech Ltd | Forming a layer |
| US5356836A (en) * | 1993-08-19 | 1994-10-18 | Industrial Technology Research Institute | Aluminum plug process |
| US5523259A (en) * | 1994-12-05 | 1996-06-04 | At&T Corp. | Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer |
| KR960026249A (ko) * | 1994-12-12 | 1996-07-22 | 윌리엄 이. 힐러 | 고압, 저온 반도체 갭 충진 프로세스 |
-
1996
- 1996-05-22 EP EP96108163A patent/EP0793268A3/en not_active Withdrawn
- 1996-05-22 KR KR19960018076A patent/KR960042974A/ko active Pending
- 1996-05-23 JP JP8128523A patent/JPH09223741A/ja active Pending
- 1996-05-29 US US08/654,810 patent/US6150252A/en not_active Expired - Lifetime
- 1996-07-10 TW TW085108325A patent/TW302513B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US6150252A (en) | 2000-11-21 |
| TW302513B (ko) | 1997-04-11 |
| EP0793268A2 (en) | 1997-09-03 |
| JPH09223741A (ja) | 1997-08-26 |
| EP0793268A3 (en) | 1999-03-03 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |