[go: up one dir, main page]

KR960039434A - Transistor having metal gate electrode and manufacturing method thereof - Google Patents

Transistor having metal gate electrode and manufacturing method thereof Download PDF

Info

Publication number
KR960039434A
KR960039434A KR1019950009451A KR19950009451A KR960039434A KR 960039434 A KR960039434 A KR 960039434A KR 1019950009451 A KR1019950009451 A KR 1019950009451A KR 19950009451 A KR19950009451 A KR 19950009451A KR 960039434 A KR960039434 A KR 960039434A
Authority
KR
South Korea
Prior art keywords
pattern
film
gate
forming
metal
Prior art date
Application number
KR1019950009451A
Other languages
Korean (ko)
Inventor
문종
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950009451A priority Critical patent/KR960039434A/en
Priority to JP8013256A priority patent/JPH08293604A/en
Publication of KR960039434A publication Critical patent/KR960039434A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

금속 게이트 전극을 갖는 트랜지스터 및 그 제조 방법.이 개시되어 있다 본 발명은 트랜지스터를 형성함에 있어서, 게이트 전극의 상부 금속막 패턴으로 비저항이 매우 작은 금속을 선택적으로 증착하여 게이트 전극의 저항을 낮추고, 하부 금속막 패턴으로는 질화계금속막을 형성하여 표면 채널을 갖는 P채널 트랜지스터를 제조하는 것이다.A transistor having a metal gate electrode and a method of manufacturing the same are disclosed. According to the present invention, in forming a transistor, a metal having a very low resistivity is selectively deposited on the upper metal film pattern of the gate electrode to lower the resistance of the gate electrode, and The metal film pattern is to form a nitride metal film to produce a P-channel transistor having a surface channel.

Description

금속 게이트 전극을 갖는 트랜지스터 및 그 제조 방법.A transistor having a metal gate electrode and a method of manufacturing the same.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도와, 제3도는 본 발명에 의해 제조된 트랜지스터를 도시한 단면도들이다.2 and 3 are cross-sectional views showing transistors manufactured by the present invention.

Claims (11)

주 표면에 소자분리를 위한 필드 산화막과 트랜지스터의 게이트 절연막이 형성된 제1도전형 반도체기판;상기 게이트 절연막 상의 일부에 제1금속막 패턴과 제2금속막 패턴이 적층되어 형성된 게이트 전극; 상기 게이트 전극의 양 측벽에 제1절연막으로 형성된 스페이서; 상기 게이트 전극 양 옆의 게이트 절연막 아래에 상기 제1도전형과 반대의 제2도전형으로 형성된 소오스/드레인 영역; 및 상기 소오스/드레인 영역이 형성된 반도체 기판 전면에 증착된 제2절연막을 구비하여 트랜지스터가 형성되는 것을 특징으로 하는 반도체 장치.A first conductive semiconductor substrate having a field oxide film and a gate insulating film of a transistor formed on a main surface thereof; Spacers formed of first insulating layers on both sidewalls of the gate electrode; A source / drain region formed under the gate insulating film on both sides of the gate electrode and formed as a second conductive type opposite to the first conductive type; And a second insulating layer deposited on the entire surface of the semiconductor substrate on which the source / drain regions are formed. 주 표면에 소자분리를 위한 필드 산화막과 트랜지스터의 게이트 절연막이 형성된 제1도전형 반도체기판; 상기 게이트 절연막 상의 일부에 폴리실리콘막 패턴, 제1금속막패턴, 및 제2금속막 패턴이 차례로 적충되어 형성된 게이트 전극; 상기 게이트 전극의 양 측벽에 제1절연막으로 형성된 스페이서; 상기 게이트 전극 양옆의 게이트 절연막 아래에 상기 제1도전형과, 반대의 제2도전형의 형성된 소오스/드레인 영역; 및 상기 소오스/드레인 영역이 형성된 반도체기판 전면에 증착된 제2절연막을 구비하여 트랜지스터가 형성되는 것을 특징으로 하는 반도체장치A first conductive semiconductor substrate having a field oxide film and a gate insulating film of a transistor formed on a main surface thereof for isolation; A gate electrode formed by partially depositing a polysilicon layer pattern, a first metal layer pattern, and a second metal layer pattern on a portion of the gate insulating layer; Spacers formed of first insulating layers on both sidewalls of the gate electrode; Source / drain regions formed under the gate insulating films on both sides of the gate electrode, and formed in a second conductive type opposite to the first conductive type; And a second insulating layer deposited on the entire surface of the semiconductor substrate on which the source / drain regions are formed. 제2항에 있어서, 상기 제1금속막 패턴은 질화텅스텐(WN), 질화타이타늄(TiN), 및 질화탄탈륨(TaN)으로 이루어진 일군에서 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체 장치.The semiconductor device of claim 2, wherein the first metal layer pattern is formed of one selected from the group consisting of tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN). 제2항에 있어서, 상기 제2금속막 패턴은 금(Au) 또는 구리(Cu)로 형성하는 것을 특징으로 하는 반도체 장치The semiconductor device of claim 2, wherein the second metal layer pattern is formed of gold (Au) or copper (Cu). 제2항에 있어서, 상기 스페이서는 질화실리콘(SiN)막으로 형성하는 것을 특징으로 하는 반도체 장치The semiconductor device according to claim 2, wherein the spacer is formed of a silicon nitride (SiN) film. 제1도전형의 반도체기판 주 표면에 필드산화마글 형성함으로써, 활성영역과 비활성영역을 한정하는 단계; 상기 활성영역과, 비활성영역이 한정된 반도체기판 전면에 게이트 절연,막 제1금속막, 그리고, 제1절연막을 차례로 형성하는 단계; 상기 활성영역 상기 일부에 상기 제1절연막과 상기 제1금속막을 패터닝 하여 제1절연막패턴과, 제1금속막 패턴으로 이루어지는 게이트 패턴을 형성하는 단계; 상기 게이트 패턴 및 상기 필드 산화막을 이온주입 마스크로 하여 제2도전형의 불순물을 제1도우즈로 이온주입함으로써 제2도전형의 저농도 소오스/드레인 영역을 형성하는 단계; 상기 게이트 패턴의 양 측벽에 제2절연막으로 이루어진 스페이서를 형성한 후 상기 제1절연막 패턴을 제거하는 단계; 상기 제1금속막 패턴 상부에만 제2금속막 패턴을 선택적으로 형성하여 상기 제1금속막 패턴과, 상기 제2금속막 패턴으로 이루어지는 게이트 전극을 형성하는 단계; 상기 게이트 전극, 상기 스페이서, 그리고, 상기 필드 산화막을 LDHS주입 마스크로 하여 제2도전형의 불순물을 상기 제1도우즈보다 많은 제2도우즈로 이온주입함으로써 제2도전형의 고,농도 소오스/드레인 영역을 형성하는 단계; 및 상기 고농도 소오스/드레인 영역이 형성된 반도체기기판 전면에 제3절연막을 증착하는 단계를 구비하여 트랜지스터를 형성하는 것을 특징으로 하는 반도체장치의 제조 방법.Forming a field oxide on the main surface of the first conductive semiconductor substrate, thereby defining an active region and an inactive region; Sequentially forming a gate insulating film, a first metal film, and a first insulating film on the entire surface of the semiconductor substrate in which the active region and the inactive region are defined; Patterning the first insulating layer and the first metal layer on the portion of the active region to form a first insulating layer pattern and a gate pattern including a first metal layer pattern; Forming a low concentration source / drain region of a second conductivity type by ion implanting a second conductivity type impurity into a first dose using the gate pattern and the field oxide film as an ion implantation mask; Removing the first insulating layer pattern after forming a spacer including a second insulating layer on both sidewalls of the gate pattern; Selectively forming a second metal film pattern only on the first metal film pattern to form a gate electrode including the first metal film pattern and the second metal film pattern; The second conductive type high, concentration source / Forming a drain region; And depositing a third insulating film on the entire surface of the semiconductor device substrate on which the high concentration source / drain regions are formed. 제1도전형의 반도체기판 주 표면에 필드 산화막을 형성함으로써, 활성영역과 비활성역을 한정하는 단계; 상기 활성영역과 비활성영역이 한정된 반도체기판 전면에 게이트 절연막, 폴리시릴콘막, 제1금속막, 그리고, 제1절연막을 차례로 형성하는 단계; 상기 활성영역 상의 일부에 상기 제1절연막, 상기 제1금속막 그리고, 상기 폴리실리콘막을 패터닝하여 제1절연막 패턴, 제1금속막패턴, 그리고, 폴리실리콘막 패턴으로 이루어지는 게이트 패턴을 형성하는 단계; 상기 게이트 패턴 및 상기 필드 산화막을 이온주입 마스크로 하여 제2도전형의 불순물을 제1도우즈로 이온주입함으로써, 제2도전형의 저농도 소오스/드레인 영역을 형성하는 단계; 상기 게이트 패턴의 양 측벽에 제2절연막으로 이루어진 스페이서를 형성한 후, 상기 제1절연막 패턴을 제거하는 단계; 상기 제1금속막 패턴 상부에만 제2금속막 패턴을 선택적으로 형성하여 상기 폴리실리콘막 패턴, 제1금속막 패턴, 그리고 상기 제2금속막 패턴으로 이루어지는 게이트 전극을 형성하는 단계; 상기 게이트 전극, 상기 스페이서, 그리고, 상기 필드 산화막을 이온주입 마스크로 하여 제2도전형의 불순물을 상기 제1도우즈보다 많은 제2도우즈로 이온주입함으로써, 제2도전형의 고,농도 소오수/드레인 영역을 형성하는 단계; 및 상기 고농도 소오스/드레인 영역이 형성된 반도체기판 전면에 제3절연막을 증착하는 단계를 구비하여 트랜지스터를 형성하는 것을 특징으로 하는 반도체장치의 제조방법.Defining an active region and an inactive region by forming a field oxide film on a main surface of the first conductive semiconductor substrate; Sequentially forming a gate insulating film, a polysilylcone film, a first metal film, and a first insulating film on the entire surface of the semiconductor substrate in which the active region and the inactive region are defined; Patterning the first insulating layer, the first metal layer, and the polysilicon layer on a portion of the active region to form a gate pattern including a first insulating layer pattern, a first metal layer pattern, and a polysilicon layer pattern; Forming a low concentration source / drain region of a second conductive type by ion implanting a second conductive type impurity into a first dose using the gate pattern and the field oxide film as an ion implantation mask; Forming a spacer including a second insulating layer on both sidewalls of the gate pattern, and then removing the first insulating layer pattern; Selectively forming a second metal film pattern only on the first metal film pattern to form a gate electrode including the polysilicon film pattern, the first metal film pattern, and the second metal film pattern; By implanting impurities of the second conductivity type into the second dose more than the first dose, using the gate electrode, the spacer, and the field oxide film as an ion implantation mask, high concentration concentration of the second conductivity type is achieved. Forming a male / drain region; And depositing a third insulating film on the entire surface of the semiconductor substrate on which the high concentration source / drain regions are formed. 제7항에 있어서, 상기 제1절연막은 플라즈마 산화막으로 형성하는 것을 특징으로 하는 반도체장치의 제조 방법.8. The method of claim 7, wherein the first insulating film is formed of a plasma oxide film. 제7항에 있어서 상기 스페이서는 질화실리콘막(SiN)으로 형성하는 것을 특징으로 라는 반도체장치의 반도체장치의 제조 방법.The method of manufacturing a semiconductor device of a semiconductor device according to claim 7, wherein the spacer is formed of a silicon nitride film (SiN). 제7항에 있어서, 상기 제1금속막은 질화타이타늄(TiN) 질화텅스텐(WN) 및 질화탄탈륨(TaN)으로 이루어진 일군에서 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 7, wherein the first metal film is formed of any one selected from the group consisting of titanium nitride (TiN) tungsten nitride (WN) and tantalum nitride (TaN). 제7항에 있어서, 상기 제2금속막은 구리(Cu)또는 금(Au)으로 형성하는 것을 특징으로 하는 반도체장치의 제조방법.8. The method of claim 7, wherein the second metal film is formed of copper (Cu) or gold (Au). ※ 참고사항: 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the original application.
KR1019950009451A 1995-04-21 1995-04-21 Transistor having metal gate electrode and manufacturing method thereof KR960039434A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019950009451A KR960039434A (en) 1995-04-21 1995-04-21 Transistor having metal gate electrode and manufacturing method thereof
JP8013256A JPH08293604A (en) 1995-04-21 1996-01-29 Transistor having metal gate electrode and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950009451A KR960039434A (en) 1995-04-21 1995-04-21 Transistor having metal gate electrode and manufacturing method thereof

Publications (1)

Publication Number Publication Date
KR960039434A true KR960039434A (en) 1996-11-25

Family

ID=19412668

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950009451A KR960039434A (en) 1995-04-21 1995-04-21 Transistor having metal gate electrode and manufacturing method thereof

Country Status (2)

Country Link
JP (1) JPH08293604A (en)
KR (1) KR960039434A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6084279A (en) * 1997-03-31 2000-07-04 Motorola Inc. Semiconductor device having a metal containing layer overlying a gate dielectric
JPH11195621A (en) * 1997-11-05 1999-07-21 Tokyo Electron Ltd Barrier metal, method of forming the same, gate electrode and method of forming the same
US6861356B2 (en) 1997-11-05 2005-03-01 Tokyo Electron Limited Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film
US7829144B2 (en) 1997-11-05 2010-11-09 Tokyo Electron Limited Method of forming a metal film for electrode
TW444257B (en) 1999-04-12 2001-07-01 Semiconductor Energy Lab Semiconductor device and method for fabricating the same
US7544595B2 (en) * 2007-01-04 2009-06-09 Freescale Semiconductor, Inc. Forming a semiconductor device having a metal electrode and structure thereof

Also Published As

Publication number Publication date
JPH08293604A (en) 1996-11-05

Similar Documents

Publication Publication Date Title
US7022559B2 (en) MOSFET gate electrodes having performance tuned work functions and methods of making same
US6147383A (en) LDD buried channel field effect semiconductor device and manufacturing method
US5516717A (en) Method for manufacturing electrostatic discharge devices
US5397715A (en) MOS transistor having increased gate-drain capacitance
JP3455452B2 (en) Semiconductor device and manufacturing method thereof
US6391750B1 (en) Method of selectively controlling contact resistance by controlling impurity concentration and silicide thickness
JPH0260217B2 (en)
KR950025920A (en) Semiconductor device manufacturing method
US4304042A (en) Self-aligned MESFETs having reduced series resistance
US6124613A (en) SOI-MOS field effect transistor that withdraws excess carrier through a carrier path silicon layer
KR970018255A (en) PROCESS FOR THE PRODUCTION OF AN INTEGRATED CMOS CIRCUIT
US4517731A (en) Double polysilicon process for fabricating CMOS integrated circuits
KR960039434A (en) Transistor having metal gate electrode and manufacturing method thereof
KR100384774B1 (en) Method for manufacturing gate in semiconductor device
KR970030676A (en) Semiconductor device and manufacturing method thereof
KR950002013A (en) Semiconductor device including thin film transistor and manufacturing method thereof
US4407004A (en) Self-aligned MESFET having reduced series resistance
JPS6334619B2 (en)
KR20030033995A (en) Method of fabricating deep sub-micron cmos source/drain with mdd and selective cvd silicide
DE3375860D1 (en) Method of manufacturing integrated mos field effect transistors with an additional interconnection level consisting of metal silicides
KR100319601B1 (en) Electrostatic discharge prevention transistor and its manufacturing method
KR960012261B1 (en) Morse-depletion-type 컽 -off transistor and method for manufacturing mask ROM cell using the transistor
JP3137774B2 (en) Semiconductor device and method of manufacturing the same
KR930020697A (en) Manufacturing method of mask rom cell
KR20010004934A (en) Method of manufacturing semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19950421

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19950421

Comment text: Request for Examination of Application

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19980429

Patent event code: PE09021S01D

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19980826

Patent event code: PE09021S01D

PC1202 Submission of document of withdrawal before decision of registration

Comment text: [Withdrawal of Procedure relating to Patent, etc.] Withdrawal (Abandonment)

Patent event code: PC12021R01D

Patent event date: 19981012

WITB Written withdrawal of application